Designing High-speed and Low Power Arithmetic Units using fine-grain 3D Die Stacking Technologies

2011 Fiscal Year Final Research Report

• Project/Area Number: 22700044
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: Tohoku University
• Principal Investigator: EGAWA Ryusuke 東北大学, サイバーサイエンスセンター, 助教 (80374990)
• Project Period (FY): 2010 – 2011
• Keywords: TSV / 低消費電力 / 演算回路 / 3次元積層技術

Research Abstract

Three-dimensional (3-D)integration technologies have been expected to overcome the limitations of conventional microprocessors, which integrated by two-dimensional (2-D)implementation technologies. However, design space of 3-D stacked circuits is not explores well so far. To clarify the design space and methods of 3-D integrated arithmetic units, this research proposes and evaluates the circuit partitioning techniques for floating point arithmetic units.

Research Products

• [Journal Article] Effects of 3-D Stacked Vector Cache on Energy Consumption (2012)
  • Author(s): Ryusuke Egawa, Yusuke Funaya, Ryu-ichi Nagaoka, Yusuke Endo, Akihiro Musa, Hiroyuki Takizawa and Hiroaki Kobayashi
  • Journal Title: in proceedings of IEEE 3DIC 2012 Volume: CDROM Pages: 1-6
  • Peer Reviewed
• [Journal Article] A Middle-Grain Circuit Partitioning Strategy for 3-D Integrated Floating-Point Multipliers (2012)
  • Author(s): Jubee Tada, Ryusuke Egawa, Kazushige Kawai, Hiroaki Kobayashi and Gensuke Goto
  • Journal Title: proceedings of IEEE 3DIC 2012 Volume: CDROM Pages: 1-6
  • Peer Reviewed
• [Journal Article] Design and Early Evaluation of 3-D Die Stacked Chip Multi-Vector (2010)
  • Author(s): Ryusuke Egawa, Yusuke Funaya, Ryuichi Nagaoka, Akihiro Musa, Hiroyuki Takizawa, and Hiroaki Kobayashi
  • Journal Title: Processors in proceedings of IEEE 3D System Integration Conference 2010 Volume: CD-ROM Pages: 1-8
  • Peer Reviewed
• [Journal Article] Cache Partitioning Strategies for 3-D Stacked Vector (2010)
  • Author(s): Yusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa, and Hiroaki Kobayashi
  • Journal Title: Processors in proceedings of IEEE 3D System Integration Conference 2010 Volume: CD-ROM Pages: 1-6
  • Peer Reviewed
• [Presentation] Designing a 3D stacked Vector Cache (2012)
  • Author(s): Ryusuke Egawa, Yusuke Endo, Jubee Tada, Hiroyuki Takizawa, Gensuke Goto, and Hiroaki Kobayashi
  • Organizer: DATE 2012 Workshop on 3D Integration . Application, Technology, Architecture, Automation and Tests
  • Place of Presentation: Dresden Germany
  • Year and Date: 2012-03-16
• [Presentation] 3次元積層技術を用いた倍精度浮動小数点加算回路設計に関する一考察 (2012)
  • Author(s): 千葉雄太, 遠藤裕亮, 船矢祐介, 江川隆輔, 滝沢寛之, 小林広明
  • Organizer: 情報処理学会東北支部研究報告会
  • Place of Presentation: 仙台
  • Year and Date: 2012-03-02
• [Presentation] 3次元積層型浮動小数点器の回路分割手法に関する研究 (2011)
  • Author(s): 河井一茂, 多田十兵衛, 江川隆輔, 小林広明, 後藤源助
  • Organizer: システムLSI設計技術研究会
  • Place of Presentation: 宮崎
  • Year and Date: 2011-11-29
• [Presentation] Effects of 3-D Stacked Vector Cache on Energy Consumption (2011)
  • Author(s): Ryusuke Egawa, Yusuke Funaya, Ryuichi Nagaoka, Akihiro Musa, Hiroyuki Takizawa, and Hiroaki Kobayashi
  • Organizer: Facing the multicore challenge II
  • Place of Presentation: Karlsruhe Germany
  • Year and Date: 2011-09-29
• [Presentation] 3次元積層型乗算器の回路分割手法に関する研究 (2010)
  • Author(s): 坂井一仁, 多田十兵衛, 江川隆輔, 小林広明, 後藤源助
  • Organizer: ICD集積回路研究会
  • Place of Presentation: 東京
  • Year and Date: 2010-12-17
• [Presentation] 3次元積層技術を用いた乗算回路設計に関する研究 (2010)
  • Author(s): 多田十兵衛, 江川隆輔, 坂井一仁, 小林広明, 後藤源助
  • Organizer: 再生可能集積システム時限研究会
  • Place of Presentation: 東京
  • Year and Date: 2010-10-15