2011 Fiscal Year Final Research Report
Designing High-speed and Low Power Arithmetic Units using fine-grain 3D Die Stacking Technologies
Project/Area Number |
22700044
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Research Category |
Grant-in-Aid for Young Scientists (B)
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Allocation Type | Single-year Grants |
Research Field |
Computer system/Network
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Research Institution | Tohoku University |
Principal Investigator |
EGAWA Ryusuke 東北大学, サイバーサイエンスセンター, 助教 (80374990)
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Project Period (FY) |
2010 – 2011
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Keywords | TSV / 低消費電力 / 演算回路 / 3次元積層技術 |
Research Abstract |
Three-dimensional (3-D)integration technologies have been expected to overcome the limitations of conventional microprocessors, which integrated by two-dimensional (2-D)implementation technologies. However, design space of 3-D stacked circuits is not explores well so far. To clarify the design space and methods of 3-D integrated arithmetic units, this research proposes and evaluates the circuit partitioning techniques for floating point arithmetic units.
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[Presentation] Designing a 3D stacked Vector Cache2012
Author(s)
Ryusuke Egawa, Yusuke Endo, Jubee Tada, Hiroyuki Takizawa, Gensuke Goto, and Hiroaki Kobayashi
Organizer
DATE 2012 Workshop on 3D Integration . Application, Technology, Architecture, Automation and Tests
Place of Presentation
Dresden Germany
Year and Date
2012-03-16
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