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2012 Fiscal Year Final Research Report

Development of high-performance and low-power consumption many-core microprocessors using nonvolatile memory elements

Research Project

  • PDF
Project/Area Number 22760248
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeSingle-year Grants
Research Field Electron device/Electronic equipment
Research InstitutionTokyo Institute of Technology

Principal Investigator

YAMAMOTO Syuuichirou  東京工業大学, 大学院・総合理工学研究科, 助教 (50313375)

Project Period (FY) 2010 – 2012
Keywordsメニーコアプロセッサ / 不揮発性メモリ / 低消費電力
Research Abstract

In this study, aiming to develop new generation high-performance and low-power microprocessors by combination of parallel processing using a many-core processor technology and ideal power-gating (PG) technology using nonvolatile memories, the better circuit configuration was presented by developing an evaluation method of power reduction efficiency during power-gating. The total power reduction effect simultaneously using dynamic voltage-frequency scaling (DVFS) and PG technology was also verified through a simulation.

  • Research Products

    (8 results)

All 2013 2012 2011

All Journal Article (4 results) (of which Peer Reviewed: 3 results) Presentation (4 results)

  • [Journal Article] Nonvolatile power-gating FPGA based on pseudo-spin-transistor architecture with spin-transfer-torque MTJs2012

    • Author(s)
      Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
    • Journal Title

      MRS Symposium Proceedings

      Volume: Vol.1430 Pages: 55-60

    • DOI

      DOI:10.1557/opl.2012.1183

    • Peer Reviewed
  • [Journal Article] Nonvolatile power-gating field-programmable gate array using nonvolatile static random access memory and nonvolatile delay flip-flops based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions2012

    • Author(s)
      Shuu'ichirou Yamamoto, Yusuke Shuto,Satoshi Sugahara
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: Vol.51 Pages: 11PB02/1-5

    • DOI

      DOI:10.1143/JJAP.51.11PB02

    • Peer Reviewed
  • [Journal Article] Nonvolatile delay flip-flop using spin-transistor architecture with spin transfer torque MTJs for power-gating systems2011

    • Author(s)
      Shuu'ichirou Yamamoto, Yusuke Shuto, Satoshi Sugahara
    • Journal Title

      Electronics Letters

      Volume: Vol.47 Pages: 1027-1028

    • DOI

      DOI:10.1049/el.2011.1807

    • Peer Reviewed
  • [Journal Article] CMOS/スピントロニクス融合技術による不揮発性ロジックシステムの展望2011

    • Author(s)
      菅原聡、周藤悠介、山本修一郎
    • Journal Title

      まぐね

      Volume: 6巻 Pages: 5-15

  • [Presentation] 疑似スピンMOSFETを用いた不揮発性デュアルポートSRAMセルの提案とNVPG応用2013

    • Author(s)
      山本修一郎
    • Organizer
      第60回応用物理学関係連合講演会
    • Place of Presentation
      神奈川工科大学、神奈川県
    • Year and Date
      2013-03-28
  • [Presentation] Nonvolatile flip-flop using pseudo-spin-transistor architecture and its power-gating applications, IEEE International Semiconductor2012

    • Author(s)
      Shuu'ichirou Yamamoto
    • Organizer
      Conference Dresden-Grenoble
    • Place of Presentation
      Minatech Campus, Grenoble, France
    • Year and Date
      2012-09-25
  • [Presentation] 疑似スピンMOSFET技術を用いたFPGAの不揮発性パワーゲーティング2012

    • Author(s)
      山本修一郎
    • Organizer
      第73回応用物理学会学術講演会
    • Place of Presentation
      愛媛大学、愛媛県
    • Year and Date
      2012-09-13
  • [Presentation] 疑似スピンMOSFETを用いた不揮発性DFF:BETにおける静的リーク電流の影響2012

    • Author(s)
      山本修一郎
    • Organizer
      第73回応用物理学会学術講演会
    • Place of Presentation
      愛媛大学、愛媛県
    • Year and Date
      2012-09-13

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Published: 2014-08-29  

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