2013 Fiscal Year Final Research Report
Logic synthesis using linear transformation and memories.
| Project/Area Number |
23300016
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Meiji University (2013)
Kyushu Institute of Technology (2011-2012) |
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Principal Investigator |
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| Co-Investigator(Renkei-kenkyūsha) |
IGUHI Yukihiro (60201307)
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| Research Collaborator |
BUTLER Jon T
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| Project Period (FY) |
2011-04-01 – 2014-03-31
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| Keywords | 線形変換 / 関数分解 / 不完全定義関数 / CAM(連想メモリ） / インデックス生成関数 / コンピュータウイルス検出 / パターンマッチング |
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| Research Abstract |
In routers for the internet and computer virus scanners, high-speed pattern matching is indispensable. In such applications, patterns must be modified frequently. To perform such operation, CAMs (Content Addressable Memories) have been used. Unfortunately, CAMs dissipate high power, and large-scale CAMs are very expensive. In this research, we developed a method to decompose an index generation function into linear and non-linear parts. Non-linear parts are realized by memories, where the number of input variables are reduced. With this method, we can implement a large-scale pattern matching circuit by using general-purpose memories. Thus, obtained circuits are low-cost and low-power.
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