Optimization techniques for asynchronous circuit design

2014 Fiscal Year Final Research Report

• Project/Area Number: 23300020
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: National Institute of Informatics
• Principal Investigator: YONEDA Tomohiro 国立情報学研究所, アーキテクチャ科学研究系, 教授 (30182851)
• Project Period (FY): 2011-04-01 – 2015-03-31
• Keywords: 非同期式回路 / 最適化 / 遅延値決定 / 配置最適化 / 設計容易化 / 遷移型制御 / 束データ方式

Outline of Final Research Achievements

Asynchronous circuits are circuits that do not need any global clock systems. Thus, they have the potential for solving a number of problems, such as clock skew problems, related to global clock systems in the synchronous circuit design. On the other hand, for practice use of asynchronous circuits, various optimization techniques specific to asynchronous circuit design are indispensable. For this purpose, we have developed (1) a tool to determine near-optimal delay values for matched delay elements that are needed for local-handshaking in the bundled-data asynchronous circuits, (2) a tool to generate scripts given to commercial Place & Route CAD tools for packing primitive registers and other instances specified by users, in order to minimize delays that affect the system performance, (3) an idea to implement transition signaling asynchronous circuits very easily using a new type of flip-flops that have multiple-clock inputs and are multiple-edge sensitive.

Free Research Field

情報学