2013 Fiscal Year Final Research Report
Highly Accurate Devect Level Estimation of SOC Chips Based on Its Layouts
| Project/Area Number |
23500063
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (C)
|
| Allocation Type | Multi-year Fund |
|---|
| Section | 一般 |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | Tokyo Metropolitan University |
|---|
Principal Investigator |
IWASAKI Kazuhiko 首都大学東京, 学術情報基盤センター, 教授 (40232649)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
ARAI Masayuki 首都大学東京, システムデザイン学部, 助教 (10336521)
ARAI Masayuki 日本大学, 生産工学部, 助教 (10336521)
|
|---|
| Project Period (FY) |
2011 – 2013
|
| Keywords | 集積回路 / 市場不良率 / VLSIテスト / レイアウト情報 / 故障カバレージ / TMR |
|---|
| Research Abstract |
A test method is developed to detect faults occurred at the wires in VLSI chips, which are not considered in the previous work. Targeting at the defects at wires, contacts, and vias, the weighted fault coverage (WFC) is proposed. Based on the criteria a new technique is presented to compress test pattern lengths while maintaining the defect level.
Triple module redundancy (TMR) has been used to improve system reliability, and the technique is applied to a pipelined processor to enhance the yield and defect level.
|
