2013 Fiscal Year Final Research Report
The robust clock and data recovery circuit for high-speed communication system
| Project/Area Number |
23560462
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Communication/Network engineering
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| Research Institution | The University of Shiga Prefecture |
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Principal Investigator |
KISHINE Keiji 滋賀県立大学, 工学部, 准教授 (20512776)
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| Project Period (FY) |
2011 – 2013
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| Keywords | LSI / アナログ回路 / フリップフロップ / メタスタビリティ / 光フロントエンド / 同期回路 / 微細デバイス / 超高速 |
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| Research Abstract |
In high speed optical communication systems, it is essential to provide robust clock and data recovery (CDR) circuits in which the quality of the system depends on those. To make clear the relation between the characteristics of devices and those of circuit operation, we propose the small signal equivalent circuit model for a CML buffer circuit and a voltage control oscillator (VCO) circuit which generates the reference clock signal. Using the equations for circuit design, we analyze the operation characteristics of the circuits and make it clear the design methodology of the circuit for achieving the robust CDR operation. To investigate the delay time generated by the CML buffer circuit and the oscillation frequency of the VCO, we fabricated those ICs by 65nm-CMOS and measure the delay and frequency. We confirm the advantage of the model and equation. Furthermore, we propose the burst mode CDR with symmetric loops. The circuit shows the instantaneous locking in HSPICE simulation.
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