• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to project page

2013 Fiscal Year Final Research Report

SoC Defect Level Reduction Based on Critical Area Sampling

Research Project

  • PDF
Project/Area Number 23700062
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeMulti-year Fund
Research Field Computer system/Network
Research InstitutionNihon University (2013)
Tokyo Metropolitan University (2011-2012)

Principal Investigator

ARAI Masayuki  日本大学, 生産工学部, 助教 (10336521)

Project Period (FY) 2011 – 2013
Keywords欠陥レベル / 重みつき故障カバレージ / VLSIテスト / クリティカルエリア
Research Abstract

In the field of semiconductor device manufacturing, there is growing problem of the gap between the defect level estimated at the design stage from the reported one for fabricated devices. In this we discuss on a accurrate defect levelestimation considering probability of faults, on the basis of logical and layout structures of target circuits. We proposed and evaluated three schemes: weighted fault coverage calculation considering multiple different defect sizes, test pattern reordering algorithm, and critical area estimation without layout data. Experimental results indicated that our proposed schemes can accurately estimate the real defect level, and also that the numbers of test patterns can be reduced.

  • Research Products

    (5 results)

All 2014 2013 2012 2011

All Journal Article (2 results) (of which Peer Reviewed: 2 results) Presentation (3 results)

  • [Journal Article] A Highly Reliable Digital Current Control using an Adaptive Sampling Method2014

    • Author(s)
      A. Saysanasongkham, M. Arai, Satoshi Fukumoto, S. Takeuchi, and K. Wada
    • Journal Title

      IEEJ Journal of Industry Applications

      Volume: Vol.3, No.4 (掲載決定)

    • Peer Reviewed
  • [Journal Article] Checkpoint Time Arrangement Rotation in Hybrid State Saving with Limited Number of Periodical Checkpoints2013

    • Author(s)
      R. Suzuki, M. Ohara, M. Arai, S. Fukumoto, and K. Iwasaki
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: Vol.E96-D, No.1 Pages: 141-145

    • Peer Reviewed
  • [Presentation] Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage2012

    • Author(s)
      M. Arai, Y. Shimizu, K. Iwasaki
    • Organizer
      2012 IEEE 21st Asian Test Symposium (ATS 2012)
    • Place of Presentation
      Niigata, Japan(pp. 89-94)
    • Year and Date
      20121119-22
  • [Presentation] Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors2011

    • Author(s)
      M. Arai, K. Iwasaki
    • Organizer
      IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2011)
    • Place of Presentation
      Pasadena, CA, USA(pp. 264-271)
    • Year and Date
      20111212-14
  • [Presentation] Self-Calibration Using Functional BIST for Transient-Fault-Tolerant Sequential Circuits in Severe Electromagnetic Environment2011

    • Author(s)
      M. Arai, A. Saysanasongkham, K. Imai,Y. Koyama, S. Fukumoto
    • Organizer
      IEEE 12th International Workshop on RTL and High-Level Testing
    • Place of Presentation
      Jaipur, India(pp. 90-93)
    • Year and Date
      20111125-26

URL: 

Published: 2015-06-25  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi