2013 Fiscal Year Final Research Report
Research on delay test techniques for ultra-low power designs
| Project/Area Number |
23700065
|
|---|
| Research Category |
Grant-in-Aid for Young Scientists (B)
|
| Allocation Type | Multi-year Fund |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | Waseda University |
|---|
Principal Investigator |
SHI YOUHUA 早稲田大学, 高等研究所, 准教授 (70409655)
|
|---|
| Project Period (FY) |
2011 – 2013
|
| Keywords | 低消費電力設計 / LSI設計 / 高信頼設計 |
|---|
| Research Abstract |
Recently, low power VLSI designs have gained a lot of research attentions from both industry and academia. Consequently, reliability becomes an important design issue in state-of-the-art low power designs. Facing this design challenge, we conducted the following researches on 1) reliable sub-threshold circuit design, 2) wire delay aware low power synthesis methods, and 3) timing error detection method to guarantee the reliability of low power VLSI designs.
|
