Development of Low Energy Processor Architecture

2014 Fiscal Year Final Research Report

• Project/Area Number: 24300012
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Partial Multi-year Fund
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Hokkaido University
• Principal Investigator: MOTOMURA MASATO 北海道大学, 情報科学研究科, 教授 (90574286)
• Co-Investigator(Kenkyū-buntansha): ASAI Tetsuya 北海道大学, 情報科学研究科, 準教授 (00312380)
• Co-Investigator(Renkei-kenkyūsha): EDAHIRO Masato 名古屋大学, 情報科学研究科, 教授 (50578854)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Keywords: リコンフィギュラブル / 組込みシステム / プロセッサ / 低電力 / 低エネルギー

Outline of Final Research Achievements

We have developed a processor architecture which features restricted dynamic reconfiguration of datapath for the sake of keeping general-purposeness and low-powerness at the same time, targeting toward embedded system application where those two features are mandatory requirement. We have named the architecure is named Control-Flow Driven Data-Flow Switching (CDDS), and conducted detailed design and test chip design. Through measurement of the fabricated test chip, we have confirmed reasonable power reduction by the proposed architecture. We have presented the results at one of major international conferences in circuit design, A-SSCC, and showed demonstration of the chip successfully.

Free Research Field

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