Optimum merging and VLSI implementation of clocking schemes for a next generation ubiquitous processor

2014 Fiscal Year Final Research Report

• Project/Area Number: 24500052
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Hirosaki University
• Principal Investigator: FUKASE Masaaki 弘前大学, 理工学研究科, 教授 (10125643)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Keywords: クロックスキーム / ウェーブパイプライン / SoC / ユビキタスプロセッサ / HCgorilla / チップ / メディアパイプライン / サイファーパイプライン

Outline of Final Research Achievements

We have developed the optimum merging technique of clocking schemes composed of a waved MFU, regular pipeline, scan test, and gated clocking. By using this method, we have improvement a ubiquitous processor, HCgorilla. The improved HCgorilla has been implemented in a 0.18 μm standard cell CMOS 7.5 mm×5 mm chip. The chip specification is as follows. The clock speed is 200 MHz. The arithmetic throughput is 0.13 GIPS. The cipher throughput is between 0.1 and 0.2 GOPS. The power dissipation is 200 mW.
We have made a PC communication system by using two LSI evaluation boards, each of which mounted an HCgorilla chip. The transmitting HCgorilla chip runs a spread spectrum routine and a cipher routine in parallel for a 1,149-byte image derived from a standard image, Pepper.bmp. Similarly, the recipient chip runs a inverse spread spectrum routine and encryption routine. The experimental result of this system has shown the practical aptitude of the HCgorilla chip for ubiquitous environments.

Free Research Field

総合領域