Studies on Fault Tolerant Sequential Circuits for a New Transient Fault Model under Highly Electromagnetic Environment

2014 Fiscal Year Final Research Report

• Project/Area Number: 24500070
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Tokyo Metropolitan University
• Principal Investigator: FUKUMOTO Satoshi 首都大学東京, システムデザイン研究科, 教授 (50247590)
• Co-Investigator(Kenkyū-buntansha): MASAYUKI Arai 日本大学, 生産工学部, 助教 (10336521)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Keywords: 高電磁環境 / 故障モデル / ディペンダブルコンピューティング / 組み込み自己テスト / 周期的な多重故障 / DC-DC コンバータ

Outline of Final Research Achievements

In this project, we have studied on fault tolerant sequential circuits for a new transient fault model under highly electromagnetic environment, which is characterized by simultaneous multiple occurrences and periodicity. The major results are as follows.
1) We have proposed a scheme to construct highly reliable processors that can tolerate against simultaneous multi-bit transient faults which occur synchronously with the switching noise. The proposed scheme applies Built-in Self Test (BIST) logic, which is implemented beside the target circuit to measure the duration of the transient faults.
2) We have proposed an adaptive sampling method for a digital control current-mode power converter circuit on an FPGA (Field Programmable Gate Array) with the PWM (Pulse Width Modulator) sawtooth carrier waveform. To avoid the switching noises, sampling timing of the AD converter will be tuned adaptively regarding the duty ratio of each switching cycle.

Free Research Field

ディペンダブルコンピューティング