Study on fully digital ratio-less SRAM design for avoiding the variability and aging effects of device characteristics

2014 Fiscal Year Final Research Report

• Project/Area Number: 24560408
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: NAKAMURA KAZUYUKI 九州工業大学, マイクロ化総合技術センター, 教授 (60336097)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Keywords: CMOS / SRAM / LSI / 素子ばらつき / 経年劣化 / マージン / レシオレス / 低電圧

Outline of Final Research Achievements

The Ratio-less SRAM technology which features fully digital operation and large operating margin for device variability and aging effect was studied. Several test chips: Mosaic SRAM cell TEGs with intentionally-added device variability for confirming the ratio-less SRAM operation, variable Vth-TEGs for emulating the threshold voltage shift, and 1Kbit SRAM test chips for comparing the minimum operating supply voltage between conventional 6T-SRAM and developed ratio-less SRAM were developed. Measured results from these test chips showed the higher immunity for device variability and the superior low supply voltage operation of ratio-less SRAM than conventional SRAMs.

Free Research Field

工学