Research on Logic Switching Activity Balanced Test for High-Quality Low-Cost LSIs

2014 Fiscal Year Final Research Report

• Project/Area Number: 24650022
• Research Category: Grant-in-Aid for Challenging Exploratory Research
• Allocation Type: Multi-year Fund
• Research Field: Computer system/Network
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: WEN Xiaoqing 九州工業大学, 大学院情報工学研究院, 教授 (20250897)
• Co-Investigator(Kenkyū-buntansha): MIYASE Kohei 九州工業大学, 情報工学研究院, 助教 (30452824) ; KAJIHARA Seiji 九州工業大学, 情報工学研究院, 教授 (80252592)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Keywords: LSIテスト / スキャンテスト電力 / クロックスキュー / 最適電力テスト / 低電力テスト / テスト品質 / IR-Drop / テストデータ

Outline of Final Research Achievements

With the ever-increasing circuit scales, ever-decreasing power supply voltages, and ever-increasing clock speeds, test quality degradation (over-test as well as under-test), which cannot be sufficiently addressed by previous solutions, has become a major problem that prevents the creation of high-quality and low-cost LSIs. In this research, we first pointed out that unbalanced switching activity around test clock paths causes severe clock skew, which is one of the major causes for test quality degradation. Based on this observation, we proposed and evaluated unique solutions for conducing vector-based test clock skew assessment as well as solutions for test generation and design-for-test for mitigating test clock skews.

Free Research Field

LSIテスト、テスト容易化設計、故障診断