Research on ultra power efficient processors with hybrid instruction pipelines

2016 Fiscal Year Final Research Report

• Project/Area Number: 24680005
• Research Category: Grant-in-Aid for Young Scientists (A)
• Allocation Type: Partial Multi-year Fund
• Research Field: Computer system/Network
• Research Institution: Nagoya University
• Principal Investigator: Shioya Ryota 名古屋大学, 工学(系)研究科(研究院), 准教授 (10619191)
• Project Period (FY): 2012-04-01 – 2017-03-31
• Keywords: マイクロアーキテクチャ / プロセッサ / 省電力化 / CPU / 高効率化

Outline of Final Research Achievements

In this research project, the researcher has studied and proposed processor architecture with in-order and out-of-order execution systems. In this architecture, most instructions are executed by a simple and power efficient in-order execution system while processing the remaining instructions by a reduced high-performance out-of-order execution system. As a result, power consumption is greatly reduced while maintaining processor performance. In this research project, proposals and evaluation results on this new architecture were published in journals and symposium papers, including IEEE/ACM International Symposium on Microarchitecture (MICRO), which is the top conference in this field.

Free Research Field

計算機アーキテクチャ