Accelerating computations using many-core architecture for FPGAs

2015 Fiscal Year Final Research Report

• Project/Area Number: 24700033
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Software
• Research Institution: Hiroshima University
• Principal Investigator: Yasuaki Ito 広島大学, 工学(系)研究科(研究院), 准教授 (40397964)
• Project Period (FY): 2012-04-01 – 2016-03-31
• Keywords: FPGA / DSPブロック / ブロックRAM / ハフ変換 / マルチコアプロセッサ

Outline of Final Research Achievements

In this research, I tried to make developing environments of many-core architecture for FPGAs. First, we proposed efficient FPGA implementations of line and circle detection that is efficiently performed with DSP blocks and block RAMs on the FPGA by separating the parameter space and arranging many processing cores. The implementations can run faster than existing methods. Using these results, we proposed a tiny general-purpose processor that supports multiple-length computation using one DSP blocks and two block RAMs and implemented it on the FPGA. Using this processor, we showed that users can develop software programs that is almost the same performance as the specific circuits.

Free Research Field

計算機工学