Transformation from Synchronous Circuits to Low Power Asynchronous Circuits

2014 Fiscal Year Final Research Report

• Project/Area Number: 24700051
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Computer system/Network
• Research Institution: The University of Aizu
• Principal Investigator: SAITO Hiroshi 会津大学, コンピュータ理工学部, 准教授 (50361671)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Keywords: 非同期式回路 / 動作合成 / 低消費電力化

Outline of Final Research Achievements

In this research, we proposed a transformation method from structural models of synchronous circuits to the ones of asynchronous circuits with bundled-data implementation. We used a commercial behavioral synthesis tool to generate structural models of synchronous circuits from an application specified by SystemC, a set of resource constraints such as clock cycle time, and a resource library. We developed a tool which is based on the proposed method. As the developed tool generates not only a structural model of a synchronous circuit but also a script used for low level synthesis tools, the design of asynchronous circuits becomes easy using the developed tool.

Free Research Field

情報学