A Power/Energy Reduction Scheme with the Cooperation between a Heterogeneous Multicore Processor and a Parallelizing Compilation Technique

2014 Fiscal Year Final Research Report

• Project/Area Number: 24700055
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Computer system/Network
• Research Institution: Waseda University (2014); The University of Electro-Communications (2012-2013)
• Principal Investigator: WADA Yasutaka 早稲田大学, 理工学術院, 助教 (40434310)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Keywords: 低消費電力化 / タスクスケジューリング / 自動並列化 / ヘテロジニアスコンピューティング / メニーコア / マルチコア

Outline of Final Research Achievements

I developed a power/energy reduction scheme realized by the cooperation between a heterogeneous manycore processor and a parallelizing compilation technique. On a heterogeneous manycore processor, which integrates multiple number/types of processor cores on a chip, it is required to schedule tasks in an parallel application to the cores on a chip considering dependencies among the tasks, characteristics of the cores, and timings to apply DVFS and Power Gating. In this research, an energy efficient task scheduling method for a parallelizing compiler was developed, and it realizes large energy reduction under the cooperation with a heterogeneous manycore architecture.

Free Research Field

計算機工学