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2013 Fiscal Year Final Research Report

Research of BIST for smart analog device

Research Project

  • PDF
Project/Area Number 24860054
Research Category

Grant-in-Aid for Research Activity Start-up

Allocation TypeSingle-year Grants
Research Field Electron device/Electronic equipment
Research InstitutionThe University of Kitakyushu

Principal Investigator

DONG QING  北九州市立大学, 国際環境工学部, 講師 (30638804)

Project Period (FY) 2012-08-31 – 2014-03-31
KeywordsアナログLSI / 自己診断システム
Research Abstract

This research introduces a built-in self test(BIST) system , which is a method of Design for Testability for analog LSI test. We explored the analog signal processing and introduced a systematic test method for analog ICs. The developed BIST generates a set of preset analog signals, and input them into each analog device in chip in turn. When a device is activated for inputs, its output signal is also sampled. The sampled signal is then quantized by an ADC, and its amplitude/frequency/phase/delay characteristics are calculated by a digital signal processing unit. These characteristics then are compared with the expected outputs by the control logic unit. The control logic unit finally judges if a circuit failure is determined. The measurement results from the test chip confirmed the testability of the introduced BIST system.

  • Research Products

    (10 results)

All 2013 2012

All Journal Article (2 results) (of which Peer Reviewed: 2 results) Presentation (8 results)

  • [Journal Article] Structured Analog Circuit and Layout Design with Transistor Array2013

    • Author(s)
      B. Yang, Q. Dong, J. Li and S. Nakatake
    • Journal Title

      IEICE

      Volume: Vol.E96-A,No.12 Pages: 2475-2486

    • Peer Reviewed
  • [Journal Article] Analog circuit synthesis with constraint generation of layout dependent effects by geometric programming2013

    • Author(s)
      Y. Zhang, B. Yang, J. Li, Q. Dong and S. Nakatake
    • Journal Title

      IEICE

      Volume: Vol.E96-A, No.12 Pages: 2487-2498

    • Peer Reviewed
  • [Presentation] Routability-driven Common-centroid Capacitor Array Generation with Signal Coupling Constraints2013

    • Author(s)
      G. Chen, J. Li, B. Yang, Q. Dong and S. Nakatake
    • Organizer
      ICDV 2013
    • Place of Presentation
      Ho Chi Minh City,Vietnam
    • Year and Date
      2013-11-16
  • [Presentation] A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements2013

    • Author(s)
      Z. Yu, G. Chen, M. Li, Q. Dong and S. Nakatake
    • Organizer
      ICDV 2013
    • Place of Presentation
      Ho Chi Minh City,Vietnam
    • Year and Date
      2013-11-16
  • [Presentation] Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects2013

    • Author(s)
      Y. Zhang, G. Chen, Q. Dong, M. Li and S. Nakatake
    • Organizer
      VLSI-SOC 2013
    • Place of Presentation
      Istanbul, Turkey
    • Year and Date
      2013-10-07
  • [Presentation] Simplified Compressed Sensing-Based Volterra Model for Broadband Wireless Power Amplifiers2013

    • Author(s)
      M. Li, G. Chen, Y. Zhang, Q. Dong, S. Nakatake
    • Organizer
      kws 2013
    • Place of Presentation
      兵庫県淡路市
    • Year and Date
      2013-07-29
  • [Presentation] A 9-bit 50MSps SAR ADC with Pre-charge VCM-based Double Input Range Algorithm2013

    • Author(s)
      G. Chen, Y. Zhang, Q. Dong, B. Yang, J. Li and S. Nakatake
    • Organizer
      GLVLSI 2013
    • Place of Presentation
      Paris, France
    • Year and Date
      2013-05-02
  • [Presentation] A Comparator Energy Model Considering Shallow Trench Isolation Stress by Geometric Programming2013

    • Author(s)
      G. Chen, Y. Zhang, B. Yang, Q. Dong, S. Nakatake
    • Organizer
      ISQED, 2013
    • Place of Presentation
      SantaClara, CA, USA
    • Year and Date
      2013-03-06
  • [Presentation] High Routability and Low Ratio Mismatch Driven Common-Centroid Capacitor Array Generation2012

    • Author(s)
      J. Li, B. Yang, Q. Dong, S. Nakatake
    • Organizer
      IEEE/ACM Workshop on Variability Modeling and Characterization (VMC) 2012
    • Place of Presentation
      Hilton San Jose, CA, USA
    • Year and Date
      2012-11-08
  • [Presentation] SRAM Macro Synthesis with Layout- dependent Effect by Geometric Programming2012

    • Author(s)
      Y. Zhang, Q. Dong, S. Nakatake
    • Organizer
      IEEE/ACM Workshop on Variability Modeling and Characterization(VMC) 2012
    • Place of Presentation
      Hilton San Jose, CA, USA
    • Year and Date
      2012-11-08

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Published: 2015-07-16  

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