Development of basic technology for achievement of metal source/drain Ge-CMOS device

2015 Fiscal Year Final Research Report

• Project/Area Number: 25249035
• Research Category: Grant-in-Aid for Scientific Research (A)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Electronic materials/Electric materials
• Research Institution: Kyushu University
• Principal Investigator: NAKASHIMA HIROSHI 九州大学, 産学連携センター, 教授 (70172301)
• Co-Investigator(Kenkyū-buntansha): NISHIDA MINORU 九州大学, 総合理工学研究院, 教授 (90183540)
• Co-Investigator(Renkei-kenkyūsha): MITSUHARA MASATOSHI 九州大学, 総合理工学研究院, 助教 (10514218) ; WANG DONG 九州大学, 総合理工学研究院, 准教授 (10419616)
• Project Period (FY): 2013-04-01 – 2016-03-31
• Keywords: Ge半導体 / 高性能デバイス / 電子材料 / 絶縁膜 / 金属/半導体コンタクト

Outline of Final Research Achievements

TiN/Ge contacts, prepared by direct sputter deposition, can alleviate the intrinsic Fermi-level pinning (FLP) position toward the conduction band edge. Investigations on both the electrical properties and interfacial structures of TiN/Ge contacts showed that an amorphous interlayer containing nitrogen played an important role in the alleviation. A thickness of a-IL was 1-2 nm. Based on these results, interfacial dipole model was proposed to explain the FLP alleviation.
The n-MOSFET was fabricated using the TiN/Ge contact as source/drain (S/D). The S/D parasitic resistance was as high as 1400 Ω. The parasitic resistance could be decreased down to 100 Ω using the embedded S/D structure.
The p-MOSFET was also fabricated using the HfGe/Ge contact as S/D. The S/D parasitic resistance was as high as 300 Ω. The parasitic resistance could be decreased down to 50 Ω using the PtGe-S/D.

Free Research Field

半導体工学