Research on Extra-Low-Power Self-Test for LSI Circuits in Implantable Medical Devices

2017 Fiscal Year Final Research Report

• Project/Area Number: 25280016
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Partial Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: WEN XIAOQING 九州工業大学, 大学院情報工学研究院, 教授 (20250897)
• Co-Investigator(Kenkyū-buntansha): 宮瀬 紘平 九州工業大学, 大学院情報工学研究院, 准教授 (30452824) ; Holst Stefan 九州工業大学, 大学院情報工学研究院, 助教 (40710322) ; 梶原 誠司 九州工業大学, 大学院情報工学研究院, 教授 (80252592)
• Research Collaborator: KINOSHITA Kozo ; Saluja K. K. ; Tehranipoor M. ; Girard P. ; AIKYO Takashi ; TAKAGI Noriaki ; Keller B. ; Varma P.
• Project Period (FY): 2013-04-01 – 2018-03-31
• Keywords: LSIテスト / スキャンテスト / テスト電力 / キャプチャ電力 / IR-Dop / クロックストレッチ / 誤テスト / テストデータ変更

Outline of Final Research Achievements

In this research, we focused on the fact that there are many invalid input transitions that do not contribute to delay fault detection in the LSI scan test, and proposed a selective input transition mask circuit that does not propagate invalid input transitions in the circuit. It was confirmed that the self test power can be drastically reduced without deteriorating the test quality by actual test-chip-based measurement as well as simulatin-based evaluation. Moreover, we succeeded in suppressing the clock stretch and improving the accuracy of the actual speed scan test by reducing the state transition around the clock signal line. The proposed method greatly contributes to the testing of LSI circuits for implantable medical devices that require ultra low power.

Free Research Field

LSIテスト