Fundamental study of high-performance, low-power transistor by hetero interface formation

2015 Fiscal Year Final Research Report

• Project/Area Number: 25289082
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Partial Multi-year Fund
• Section: 一般
• Research Field: Electronic materials/Electric materials
• Research Institution: Tohoku University
• Principal Investigator: NIWA Masaaki 東北大学, 国際集積エレクトロニクス研究開発センター, 教授 (90608936)
• Co-Investigator(Kenkyū-buntansha): HASUNUMA Ryu 筑波大学, 数理物質科学研究科, 准教授 (90372341) ; SHIRAISHI Kenji 名古屋大学, 工学研究科, 教授 (20334039) ; SATO Soshi 東北大学, 国際集積エレクトロニクス研究開発センター, 助教 (80649749)
• Co-Investigator(Renkei-kenkyūsha): YAMABE Kikuo 筑波大学, 数理物質科学研究科, 教授 (10272171)
• Project Period (FY): 2013-04-01 – 2016-03-31
• Keywords: 絶縁破壊機構 / 表面・界面物理解析 / 信頼性物理 / ゲート絶縁膜 / 結晶性 / ヘテロエピタキシャル成長 / 透過型電子顕微鏡

Outline of Final Research Achievements

In regard to the current serious energy issue, especially from the electric energy point of view, fundamental study of high-performance, low-power MOSFET　using wide band gap semiconductor, i.e., 1) Electric breakdown of Al, Ploy Si/SiO2/SiC capacitors and 2) Crystallinity of GaN/BP/Si(001) heterostructure　was performed.
In case of 1), characteristic carpet-bombing-like concaves were observed by the dielectric breakdown and its developmental mechanism was clarified by means of electrical and physical analyses. This phenomenon is not observed for the conventional Si-MOS capacitors. For 2), number of defects of the crystal BP on Si(001) was found to decreased with increasing its thickness. And it was confirmed experimentaly that high quality BP buffer layer with minimized defets is imperative to obtain a high quality GaN crystal on the BP buffer layer on Si(001).

Free Research Field

電子デバイス界面制御、評価