Computer architecture for high performance and low power consumption

2015 Fiscal Year Final Research Report

• Project/Area Number: 25330057
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Nagoya University
• Principal Investigator: Ando Hideki 名古屋大学, 工学(系)研究科(研究院), 教授 (40293667)
• Project Period (FY): 2013-04-01 – 2016-03-31
• Keywords: コンピュータ・アーキテクチャ

Outline of Final Research Achievements

In this study, I have proposed a scheme called dynamic instruction window resizing to overcome the memory wall, which limits the performance improvement of processors. My evaluation results using SPEC2006 benchmark programs show that this scheme successfully improves the performance of a processor by 21% on average. We have also proposed a scheme called issue queue double-stage tag comparison to reduce the power consumption of a processor. My evaluation results
using SPEC2006 benchmark programs show that this scheme successfully reduces the power consumption of the tag comparison circuit, which is a maximum consumer in the issue queue, by 50% with only 1% performance degradation on average.

Free Research Field

コンピュータ・アーキテクチャ