Improving Coverage Driven Verification for Hardware Using Machine Learning

2015 Fiscal Year Final Research Report

• Project/Area Number: 25330061
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Shimane University
• Principal Investigator: Hamaguchi Kiyoharu 島根大学, 総合理工学研究科(研究院), 教授 (80238055)
• Project Period (FY): 2013-04-01 – 2016-03-31
• Keywords: シミュレーション検証 / SATソルバ / カバレッジ駆動型検証 / ベイジアンネットワーク

Outline of Final Research Achievements

In design process of microcomputers or FPGA devices, more efficient design verification is demanding. In simulation-based verification, the method for improving a quantitative metric called coverage is called coverage driven verification. In this research we uses machine learning for Bayesian networks for generating input patterns for simulation. Focusing on simulation parameters for the transition of signals in the design, our proposed method shows that coverage can be improved more quickly than the other existing methods.

Free Research Field

ハードウェアの設計支援技術