2016 Fiscal Year Final Research Report
Study on Test and Design for Reliable and Accurate Stochastic Logic Circuits
| Project/Area Number |
25330072
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Hiroshima City University |
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Principal Investigator |
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| Project Period (FY) |
2013-04-01 – 2017-03-31
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| Keywords | ディペンダブルコンピューティング / ストカスティックコンピューティング / 論理回路設計 / フォールトトレランス |
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| Outline of Final Research Achievements |
Stochastic logic (SL), which is an approximate computation with probabilities, has attracted attention owing to its high fault tolerance. In this study, we have proposed several effective design methodologies for SL circuits from the two points of view. One point is accuracy, area size and acceleration of SL circuits. Based on this point, three methods has been developed. For example, a design method for SL-based digital filter circuits can produce about 1/3 smaller circuits without losing their accuracy, compared with a conventional design method. The other point is reliability; we derived two methods for designing reliable SL circuits. These proposed methods can improve the reliability of weak parts in SL circuits for multiply-accumulate operation and some primary operations.
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| Free Research Field |
ディペンダブルコンピューティング
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