2015 Fiscal Year Final Research Report
Research on easily self-testable arithmetic circuits with online error detection capability
| Project/Area Number |
25730033
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
|
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| Research Institution | Chukyo University |
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Principal Investigator |
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| Project Period (FY) |
2013-04-01 – 2016-03-31
|
| Keywords | 算術演算回路 / VLSIのテスト / オンライン誤り検出 / 乗算回路 / 加算回路 |
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| Outline of Final Research Achievements |
We have proposed an online error detectable low-overhead parallel prefix adder, and an easily self-testable carry select adder with online error detection capability. For floating-point operations, we have proposed an online error detectable floating-point multiplier utilizing partial duplication instead of full duplication for multiplication of significands, and it detects any erroneous output with error larger than one unit in the last place (1 ulp) of the significand. We have also proposed an online error detectable floating-point arithmetic unit which can detect erroneous outputs caused by erroneous rounding by two-stage residue checking. In addition, we have proposed a three-operand complex multiplier with online error detection capability.
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| Free Research Field |
計算機システム
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