2016 Fiscal Year Final Research Report
Complementary vertical tunnel FET aiming for low voltage and high speed operation by heterostructure design and miniaturization
| Project/Area Number |
26249046
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
鈴木 寿一 北陸先端科学技術大学院大学, 学内共同利用施設等, 教授 (80362028)
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| Co-Investigator(Renkei-kenkyūsha) |
KANAZAWA Toru 東京工業大学, 工学院, 助教 (40514922)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Keywords | トンネルFET / ヘテロ接合 / 化合物半導体 |
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| Outline of Final Research Achievements |
In order to improve the performance of the integrated circuit, it is necessary to simultaneously perform high on-current / low off-current / low power supply voltage. To realize that, research and development of a hetero structure and a fine multi gate structure combined with different materials for a tunnel FET (TFET) which operates on a different principle from the conventional one is necessary.
Based on the theoretical calculation, a double gate structure InGaAs / GaAsSb tunnel FET with a width of 20 nm was fabricated, and the subthreshold characteristic showing the change in current with respect to the gate voltage was confirmed to be 68 mV / dec, which is lower than the conventional one.
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| Free Research Field |
化合物半導体電子デバイス
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