Three dimensional FPGA architecture and its design method

2016 Fiscal Year Final Research Report

• Project/Area Number: 26730028
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Computer system
• Research Institution: Kumamoto University
• Principal Investigator: Amagasaki Motoki 熊本大学, 大学院先端科学研究部(工), 助教 (50467974)
• Project Period (FY): 2014-04-01 – 2017-03-31
• Keywords: 3D-FPGA / face-down / face-up / TSV

Outline of Final Research Achievements

3D FPGAs are expected to offer higher logic density, delay and low power by utilizing 3D integrated circuit technology. However, because TSVs for conventional 3D FPGA interlayer connections have a large area overhead, there is an inherent tradeoff between connectivity and small size. To find a balance between cost and performance, and to explore 3D FPGAs with realistic 3D integration processes, we propose two types of 3D FPGA and construct design tool sets for architecture exploration. In previous research, we created a TSV-free 3D FPGA with a face-down integration method; however, this was limited to two layers. In this study, we discuss the face-up stacking of several face-down stacked FPGAs. To minimize the number of TSVs, we placed TSVs peripheral to the FPGAs for 3D-FPGA with 4 layers. According to our results, a 2-layer 3D FPGA has reasonable performance when limiting the design to two layers, but a 4layer 3D FPGA is a better choice when area is emphasized.

Free Research Field

計算機アーキテクチャ