| Project/Area Number |
13555090
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
MASU Kazuya Tokyo Institute of Technology, Precision and Intelligence Lab., Professor, 精密工学研究所, 教授 (20157192)
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| Project Period (FY) |
2001 – 2002
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| Project Status |
Completed (Fiscal Year 2002)
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| Budget Amount *help |
¥14,000,000 (Direct Cost: ¥14,000,000)
Fiscal Year 2002: ¥2,900,000 (Direct Cost: ¥2,900,000)
Fiscal Year 2001: ¥11,100,000 (Direct Cost: ¥11,100,000)
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| Keywords | ULSI / Silicon / Interconnect / Electromigration / High Speed Signal Processing / Transmission Line Interconnect |
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| Research Abstract |
The two major reliability issues of Si CMOS ULSI are (1) reliability of ultra thin gate insulator, and (2) EM(electromigration) endurance when a high density current is flowed through ultra fine interconnects. This research project is relating to the second issue. In 100nm and sub-100nm Si CMOS ULSIs, the EM issue is critical at the fine interconnect with several tens μm length. The conventional EM endurance is measured using DC current. On the other, in real ULSI, GHz pulse signal is flowed through the fine interconnect. It has been said that the EM endurance is improved at high frequency current condition. However, quantitative EM life time is not clarified. The purpose of this research project is to develop the interconnect structure which can measure GHz EM endurance. The measurement system for GHz signal through ULSI interconnect has been established. Using a 3D electromagnetic simulation, the transmission line interconnect has been designed, fabricated, and evaluated. Furthermore, driver circuit which drives the transmission line interconnect has been designed. From these results, the evaluation technology for GHz EM endurance has been established.
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