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Hardware Design Methodology to Utilize Next-Generation Device That May Not Work Properly

Research Project

Project/Area Number 15H02679
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system
Research InstitutionRitsumeikan University

Principal Investigator

YAMASHITA Shigeru  立命館大学, 情報理工学部, 教授 (30362833)

Co-Investigator(Kenkyū-buntansha) 原 祐子  東京工業大学, 工学院, 准教授 (20640999)
冨山 宏之  立命館大学, 理工学部, 教授 (80362292)
Project Period (FY) 2015-04-01 – 2020-03-31
Project Status Completed (Fiscal Year 2019)
Budget Amount *help
¥17,810,000 (Direct Cost: ¥13,700,000、Indirect Cost: ¥4,110,000)
Fiscal Year 2019: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2018: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2017: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2016: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2015: ¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000)
KeywordsApproximate Computing / Stochastic Computing / 設計理論 / 確率的な回路 / Probabilistic Circuit / 高位合成 / 高信頼設計 / LSI設計 / 信頼性の低い素子 / 確率的な動作をする回路
Outline of Final Research Achievements

When we design a circuit with unreliable devices, the circuit may output wrong values for certain input patterns. Even so, when such errors can be ignored, we can still use such circuits. Thus, we studied many aspects of Approximate Computing to find various results concerning how we can tolerate some errors. For example, we found an efficient way to design approximate multipliers that have a good trade-off between an image discrimination rate and hardware costs (area and speed) when we develop hardware CNNs for recognizing handwritten characters. Moreover, we also develop an design method for Stochastic Computing such that we can decrease the hardware cost while we keep the calculation errors low.

Academic Significance and Societal Importance of the Research Achievements

信頼性は低いが超小型・超低消費電力などの特性を持つ次世代の素子が将来的に利用できるようになった時には、それを十分に使いこなす設計技術が必要である。具体的には、ばらつきがある素子を利用するために、誤動作する可能性がある回路をそのエラーを許容しながらどのように利用するかという設計指針が必要となる。そのために、本研究により得られたApproximate ComputingやStochastic Computingの分野における様々な設計指針が有用となると期待できる。

Report

(6 results)
  • 2019 Annual Research Report   Final Research Report ( PDF )
  • 2018 Annual Research Report
  • 2017 Annual Research Report
  • 2016 Annual Research Report
  • 2015 Annual Research Report
  • Research Products

    (49 results)

All 2020 2019 2018 2017 2016 2015 Other

All Int'l Joint Research (2 results) Journal Article (19 results) (of which Int'l Joint Research: 3 results,  Peer Reviewed: 19 results,  Open Access: 1 results,  Acknowledgement Compliant: 2 results) Presentation (28 results) (of which Int'l Joint Research: 13 results,  Invited: 5 results)

  • [Int'l Joint Research] University of Toronto(カナダ)

    • Related Report
      2015 Annual Research Report
  • [Int'l Joint Research] National Tsing Hua University(台湾)

    • Related Report
      2015 Annual Research Report
  • [Journal Article] Efficient Methods to Generate Constant SNs with Considering Trade-Off between Error and Overhead and Its Evaluation2020

    • Author(s)
      Yudai Sakamoto, Shigeru Yamashita,
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E103.D Issue: 2 Pages: 321-328

    • DOI

      10.1587/transinf.2018EDP7435

    • NAID

      130007793565

    • ISSN
      0916-8532, 1745-1361
    • Year and Date
      2020-02-01
    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Digital Bio-Inspired Satisfiability Solver Leveraging Fluctuations2020

    • Author(s)
      Yuko Hara-Azumi, Naoki Takeuchi, Kazuaki Hara, Masashi Aono
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: vol. 59, no. 4 Issue: 4 Pages: 1-10

    • DOI

      10.35848/1347-4065/ab7ade

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed / Open Access
  • [Journal Article] Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments2019

    • Author(s)
      Chin-Heng Liu, Chia-Chun Lin, Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, Sigeru Yamashita
    • Journal Title

      IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

      Volume: vol. 38, no. 12 Issue: 12 Pages: 2284-2297

    • DOI

      10.1109/tcad.2018.2878181

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed / Int'l Joint Research
  • [Journal Article] Scheduling of Malleable Tasks with DMA-based Communication2019

    • Author(s)
      Kana Shimada, Takuma Hikida, Hiroki Nishikawa, Ittetsu Taniguchi, Hiroyuki Tomiyama
    • Journal Title

      International SoC Design Conference

      Volume: ISOCC2019 Pages: 48-49

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Function-Level Module Sharing in High-Level Synthesis2019

    • Author(s)
      Ryohei Nozaki, Hiroki Nishikawa, Ittetsu Taniguchi, Hiroyuki Tomiyama
    • Journal Title

      International SoC Design Conference

      Volume: ISOCC2019 Pages: 50-51

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Maximum Error-Aware Design of Approximate Array Multipliers2019

    • Author(s)
      Kenta Shirane, Takahiro Yamamoto, Ittetsu Taniguchi, Yuko Hara-Azumi, Shigeru Yamashita, Hiroyuki Tomiyama
    • Journal Title

      International SoC Design Conference

      Volume: ISOCC2019 Pages: 73-74

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A Case Study on Design of Approximate Multipliers for MNIST CNN2019

    • Author(s)
      Kenta Shirane, Takahiro Yamamoto, Hiroyuki Tomiyama
    • Journal Title

      Workshop on Synthesis And System Integration of Mixed Information Technologies

      Volume: SASIMI19 Pages: 251-255

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A New Approach to Express Stochastic Numbers2019

    • Author(s)
      Yukino Watanabe, Shigeru Yamashita
    • Journal Title

      Workshop on Synthesis And System Integration of Mixed Information Technologies

      Volume: SASIMI19 Pages: 95-98

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A Layout Design Method of QCA without Fixing Data Flow2019

    • Author(s)
      Kazuki Morita, Wakaki Hattori, Shigeru Yamashita
    • Journal Title

      Workshop on Synthesis And System Integration of Mixed Information Technologies

      Volume: SASIMI19 Pages: 256-261

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Effect of Reducing the Bit Length of LFSRs for SC2019

    • Author(s)
      Yudai Sakamoto, Shigeru Yamashita
    • Journal Title

      Workshop on Synthesis And System Integration of Mixed Information Technologies

      Volume: SASIMI19 Pages: 280-285

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Journal Article] On Optimization Methods for Decision Diagrams to Represent Probabilities2018

    • Author(s)
      Kodai Abe, Kentaro Haneda, Shigeru Yamashita
    • Journal Title

      Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies

      Volume: SASIMI2018 Pages: 106-111

    • Related Report
      2017 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Stochastic Number Generation with the Minimum Inputs2017

    • Author(s)
      Ritsuko Muguruma, Shigeru Yamashita
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E100.A Issue: 8 Pages: 1661-1671

    • DOI

      10.1587/transfun.E100.A.1661

    • NAID

      130005875851

    • ISSN
      0916-8508, 1745-1337
    • Related Report
      2017 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers2017

    • Author(s)
      Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E100.A Issue: 7 Pages: 1496-1499

    • DOI

      10.1587/transfun.E100.A.1496

    • NAID

      130007311789

    • ISSN
      0916-8508, 1745-1337
    • Related Report
      2017 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A Systematic Methodology for Design and Analysis of Approximate Array Multipliers2016

    • Author(s)
      Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi
    • Journal Title

      Asia Pacific Conference on Circuits and Systems

      Volume: 2016 Pages: 352-354

    • DOI

      10.1109/apccas.2016.7803973

    • Related Report
      2016 Annual Research Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Journal Article] A Decision Diagram to Analyze Probabilistic Behavior of Circuits2016

    • Author(s)
      Kodai Abe, Shigeru Yamshita
    • Journal Title

      Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies

      Volume: SASIMI 2016

    • Related Report
      2016 Annual Research Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Journal Article] Area/Latency Optimized Early Output Asynchronous Full Adders and RelativeTimed Ripple Carry Adders2016

    • Author(s)
      P. Balasubramanian, S. Yamashita,
    • Journal Title

      SpringerPlus

      Volume: 5(1) Issue: 1 Pages: 1-26

    • DOI

      10.1186/s40064-016-2074-z

    • Related Report
      2016 Annual Research Report
    • Peer Reviewed / Int'l Joint Research
  • [Journal Article] Effect of LFSR Seeding, Scrambling and Feedback Polynomial on Stochastic Computing Accuracyffect of LFSR Seeding, Scrambling and Feedback Polynomial on Stochastic Computing Accuracy2016

    • Author(s)
      Jason H. Anderson, Yuko Hara-Azumi, Shigeru Yamashita
    • Journal Title

      Design, Automation & Test in Europe (DATE)

      Volume: 2016 Pages: 1550-1555

    • Related Report
      2015 Annual Research Report
    • Peer Reviewed / Int'l Joint Research
  • [Journal Article] Stochastic Number Generation with Few Inputs2016

    • Author(s)
      Ritsuko Muguruma and Shigeru Yamashita
    • Journal Title

      29th International Conference on VLSI Design

      Volume: 2016 Pages: 128-133

    • DOI

      10.1109/vlsid.2016.83

    • Related Report
      2015 Annual Research Report
    • Peer Reviewed
  • [Journal Article] An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips2015

    • Author(s)
      Trung Anh Dinh, Shigeru Yamashita and Tsung-Yi Ho
    • Journal Title

      IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

      Volume: 34 Issue: 4 Pages: 629-641

    • DOI

      10.1109/tcad.2015.2394502

    • Related Report
      2015 Annual Research Report
    • Peer Reviewed
  • [Presentation] 手書き文字認識CNNに対する近似乗算器の設計探索2019

    • Author(s)
      白根健太, 山元貴普, 冨山宏之
    • Organizer
      情報処理学会SLDM/EMB/電子情報通信学会VLD/DC研究会
    • Related Report
      2019 Annual Research Report
  • [Presentation] Reducing the Overhead of Stochastic Number Generators Without Increasing Error2019

    • Author(s)
      Yudai Sakamoto, Shigeru Yamashita
    • Organizer
      32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID 2019)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 近似乗算器の手書き文字認識CNNへの適用事例2019

    • Author(s)
      白根健太, 山元貴普, 谷口一徹, 冨山宏之
    • Organizer
      電子情報通信学会VLD研究会
    • Related Report
      2018 Annual Research Report
  • [Presentation] 演算誤差と回路面積のトレードオフを考慮したStochastic Numberの生成手法2018

    • Author(s)
      坂本雄大, 山下茂
    • Organizer
      デザインガイア2018
    • Related Report
      2018 Annual Research Report
  • [Presentation] Approximate Computingを利用した配列型乗算器の遅延故障への対処法2018

    • Author(s)
      渡邊結希乃, 山下茂
    • Organizer
      2018年度情報処理学会関西支部支部大会
    • Related Report
      2018 Annual Research Report
  • [Presentation] SCの定数生成におけるエラー率を考慮した面積コスト削減手法2018

    • Author(s)
      坂本雄大, 山下茂
    • Organizer
      2018年度情報処理学会関西支部支部大会
    • Related Report
      2018 Annual Research Report
  • [Presentation] A Systematic Approach to Design of Approximate Array Multipliers2018

    • Author(s)
      Takahiro Yamamoto, Kenta Shirane, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi
    • Organizer
      2018 Taiwan and Japan Conference on Circuits and Systems (TJCAS'18)
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 近似データ再利用に基づく組込みシステムのアクセラレータ設計2018

    • Author(s)
      原祐子
    • Organizer
      2018年電子情報通信学会ソサイエティ大会
    • Related Report
      2018 Annual Research Report
    • Invited
  • [Presentation] Stochastic Computingにおける相関の許容によるSNGの削減2017

    • Author(s)
      渡邉 朗弘,山下 茂
    • Organizer
      ETNET2017
    • Place of Presentation
      具志川農村環境改善センター(沖縄県・久米島町)
    • Year and Date
      2017-03-09
    • Related Report
      2016 Annual Research Report
  • [Presentation] Stochastic Computingにおけるマルチプレクサの制御入力として複雑な式を用いる回路設計2017

    • Author(s)
      壷阪 幸輝,山下 茂
    • Organizer
      ETNET2017
    • Place of Presentation
      具志川農村環境改善センター(沖縄県・久米島町)
    • Year and Date
      2017-03-09
    • Related Report
      2016 Annual Research Report
  • [Presentation] 試料生成における汚染問題を考慮したDMFB合成手法2017

    • Author(s)
      北川 大樹,山下 茂
    • Organizer
      ETNET2017
    • Place of Presentation
      具志川農村環境改善センター(沖縄県・久米島町)
    • Year and Date
      2017-03-09
    • Related Report
      2016 Annual Research Report
  • [Presentation] Systematic Design of Approximate Array Multipliers with Different Accuracy2017

    • Author(s)
      Takahiro Yamamoto, Hiroyuki Tomiyama, Ittetsu Taniguchi, Shigeru Yamashita, Yuko Hara-Azumi
    • Organizer
      International Workshop on Highly Efficient Neural Networks Design
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Efficient Data Clustering by Architectural Perforation2017

    • Author(s)
      Fransiscus Marcel Satria and Yuko Hara-Azumi
    • Organizer
      Multidisciplinary International Student Workshop
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Exploration of Hardware-Implementation-Aware Amoeba-SAT Solver2017

    • Author(s)
      Nguyen Hoang Ngoc Anh and Yuko Hara-Azumi
    • Organizer
      Multidisciplinary International Student Workshop
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Scalable FPGA Implementation of Amoeba-SAT Solver2017

    • Author(s)
      Kazuaki Hara and Yuko Hara-Azumi
    • Organizer
      Multidisciplinary International Student Workshop
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Architectural Approach on Approximate Computing for Media Processing2016

    • Author(s)
      Yuko Hara-Azumi, Hisashi Osawa, and Tanvir Ahmed
    • Organizer
      International Symposium on Nonlinear Theory and Its Applications (NOLTA)
    • Place of Presentation
      ニューウェルシティ湯河原(静岡県・熱海市)
    • Year and Date
      2016-11-29
    • Related Report
      2016 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] Approximate Computingに基づいたデータ再利用型組込みプロセッサ2016

    • Author(s)
      大澤 永始,Tanvir Ahmed,原 祐子
    • Organizer
      LSIとシステムのワークショップ
    • Place of Presentation
      東京大学 生産技術研究所 (東京都目黒区)
    • Year and Date
      2016-05-17
    • Related Report
      2016 Annual Research Report
  • [Presentation] 配列型近似乗算器の設計と解析2016

    • Author(s)
      山元貴普, 谷口一徹, 冨山宏之, 山下茂, 原祐子
    • Organizer
      回路とシステムワークショップ
    • Place of Presentation
      北九州国際会議場(福岡県・北九州市)
    • Year and Date
      2016-05-13
    • Related Report
      2016 Annual Research Report 2015 Annual Research Report
  • [Presentation] Fast and Simple Netlist-level Fault-Injection Framework on FPGA2016

    • Author(s)
      Kazuki Zenba, Tanvir Ahmed,Yuko Hara-Azumi
    • Organizer
      IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIX
    • Place of Presentation
      横浜情報文化センター(神奈川県・横浜市)
    • Year and Date
      2016-04-21
    • Related Report
      2015 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Partially-Programmable Circuit を 用いた遅延故障の回避手法2016

    • Author(s)
      春日井 貴通,山下 茂,原 祐子
    • Organizer
      ETNET2016
    • Place of Presentation
      福江文化会館(長崎県・五島市)
    • Year and Date
      2016-03-25
    • Related Report
      2015 Annual Research Report
  • [Presentation] RQFPゲートを用いた超低消費電力AQFP論理回路の設計手法2016

    • Author(s)
      松本 涼平,山下 茂,竹内 尚輝
    • Organizer
      ETNET2016
    • Place of Presentation
      福江文化会館(長崎県・五島市)
    • Year and Date
      2016-03-25
    • Related Report
      2015 Annual Research Report
  • [Presentation] Approximate Computing を用いた乗算器の実装および検証2016

    • Author(s)
      後藤 敏宏,山下 茂
    • Organizer
      ETNET2016
    • Place of Presentation
      福江文化会館(長崎県・五島市)
    • Year and Date
      2016-03-25
    • Related Report
      2015 Annual Research Report
  • [Presentation] Pin-Count Reduction Techniques for Logic Integrated Digital Microfluidic Biochips2016

    • Author(s)
      Shigeru Yamashita
    • Organizer
      29th International Conference on VLSI Design
    • Place of Presentation
      Kolkata (India)
    • Year and Date
      2016-01-05
    • Related Report
      2015 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] Stochastic Computingに用いる定数を近似する回路の合成手法2015

    • Author(s)
      壷阪 幸輝、山下 茂
    • Organizer
      2015 年度情報処理学会関西支部 支部大会
    • Place of Presentation
      大阪大学中之島センター(大阪府・大阪市)
    • Year and Date
      2015-09-28
    • Related Report
      2015 Annual Research Report
  • [Presentation] Instruction-Set Extension of Embedded Microprocessor for Timing Speculation2015

    • Author(s)
      Yuko Hara-Azumi, Tanvir Ahmed, Takuya Azumi, Nikil D. Dutt
    • Organizer
      International Conference on Integrated Circuits, Design, and Verification (ICDV)
    • Place of Presentation
      Ho Chi Minh City (Vietnam)
    • Year and Date
      2015-08-11
    • Related Report
      2015 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] Timing Speculation-Aware Instruction Set Extension for Resource-Constrained Embedded Systems2015

    • Author(s)
      Tanvir Ahmed, Yuko Hara-Azumi
    • Organizer
      Application-specific Systems, Architectures and Processors (ASAP)
    • Place of Presentation
      Toronto (Canada)
    • Year and Date
      2015-07-27
    • Related Report
      2015 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Revisiting Function Inlining in FPGA High-Level Synthesi2015

    • Author(s)
      Yohei Onishi, Ittetsu Taniguchi, Hiroyuki Tomiyama
    • Organizer
      International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
    • Place of Presentation
      Seoul (Korea)
    • Year and Date
      2015-06-30
    • Related Report
      2015 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Partially-Programmable Circuit: New Flexible Method for Fault-Tolerance Improvement and Its Application2015

    • Author(s)
      Yuko Hara-Azumi
    • Organizer
      Electronic System Level Synthesis Conference (ESLsyn)
    • Place of Presentation
      San Fransisco (USA)
    • Year and Date
      2015-06-10
    • Related Report
      2015 Annual Research Report
    • Int'l Joint Research / Invited

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Published: 2015-04-16   Modified: 2022-11-04  

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