| Project/Area Number |
18K11218
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Review Section |
Basic Section 60040:Computer system-related
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| Research Institution | The University of Tokushima |
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Principal Investigator |
YOTSUYANAGI Hiroyuki 徳島大学, 大学院社会産業理工学研究部(理工学域), 准教授 (90304550)
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| Project Period (FY) |
2018-04-01 – 2021-03-31
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| Project Status |
Completed (Fiscal Year 2020)
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| Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2020: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2019: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2018: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | VLSIの検査技術 / 検査容易化設計 / ３次元積層IC / 遅延故障 / LSIテスト / ディペンダブル・コンピューティング / ディペンダブルコンピューティング / VLSIのテスト技術 / VLSIの検査容易化設計 / 故障検出 |
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| Outline of Final Research Achievements |
In this research, we proposed some circuits and procedures for test pattern generation and propagation for design-for-testability circuit that detects faults at interconnects of 3D stacked ICs. For detecting delay caused by fault and aging effects, we evaluated and enhanced the design-for-testability circuits for delay faults. The proposed methods include a design of a delay gate that has a small difference caused by test input signal transitions, a test pattern generation for reducing test application time by selecting multiple paths during some test patterns, and a design-for-testability circuit that has bypass operation during setting control signals and observing test results using boundary scan design for reducing test clocks.
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| Academic Significance and Societal Importance of the Research Achievements |
3次元積層ICには，配線が短く高速動作が可能，パッケージの小型化が可能，低消費電力であることなどの利点がある。提案した各手法によりIC間接続に発生する遅延を生じる検査困難な遅延故障のテストが可能となり，またそのテスト時間を抑えるテスト入力生成およびテスト容易化設計手法の適用により積層ICの製造コスト削減に寄与すると考えられる。
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