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Over 100 GHz Time-Space Superconductor Computing for Post-Moore Era

Research Project

Project/Area Number 19H01105
Research Category

Grant-in-Aid for Scientific Research (A)

Allocation TypeSingle-year Grants
Section一般
Review Section Medium-sized Section 60:Information science, computer engineering, and related fields
Research InstitutionKyushu University

Principal Investigator

Inoue Koji  九州大学, システム情報科学研究院, 教授 (80341410)

Co-Investigator(Kenkyū-buntansha) 松永 裕介  九州大学, システム情報科学研究院, 准教授 (00336059)
田中 雅光  名古屋大学, 工学研究科, 助教 (10377864)
岩下 武史  北海道大学, 情報基盤センター, 教授 (30324685)
谷本 輝夫  九州大学, システム情報科学研究院, 助教 (60826353)
小野 貴継  九州大学, システムLSI研究センター, 准教授 (80756239)
Project Period (FY) 2019-04-01 – 2022-03-31
Project Status Completed (Fiscal Year 2021)
Budget Amount *help
¥44,980,000 (Direct Cost: ¥34,600,000、Indirect Cost: ¥10,380,000)
Fiscal Year 2021: ¥13,650,000 (Direct Cost: ¥10,500,000、Indirect Cost: ¥3,150,000)
Fiscal Year 2020: ¥16,900,000 (Direct Cost: ¥13,000,000、Indirect Cost: ¥3,900,000)
Fiscal Year 2019: ¥14,430,000 (Direct Cost: ¥11,100,000、Indirect Cost: ¥3,330,000)
Keywordsコンピュータアーキテクチャ / 超伝導コンピューティング / マイクロプロセッサ / プロセッサ / アーキテクチャ
Outline of Research at the Start

本研究では,①空間計算型SFQプロセッサ技術の確立,②時間計算型SFQプロセッサ技術の確立,③100 GHz級SFQ回路を対象とする設計自動化技術の確立,④時空間超伝導コンピューティング法の確立,の4つの研究課題を設定する.これらを遂行することにより,単一磁束量子回路を用いた 100 GHz 級超高速ビット並列型プロセッサを世界に先駆けて実現する.汎用空間方向処理とレースロジック方式による時間方向処理を融合した新しい超伝導コンピューティング・アーキテクチャ技術を確立し,ポストムーア時代を支えるコンピューティング基盤へとつなげる.

Outline of Final Research Achievements

Aiming to realize a processor with ultra-high speed and ultra-low power consumption using single flux quantum (SFQ) logics, we have proposed novel architectures that consider the device and circuit characteristics. In addition, through chip prototyping, we have successfully demonstrated many SFQ chips, such as the world's first 30 GHz bit-parallel gate-level pipelined processor and its improved version with 50 GHz operation, a variable bit-width vector arithmetic unit, and a 100 GHz circuit. In addition, we have organized and generalized the design methodology of SFQ ultra-high-speed circuits.

Academic Significance and Societal Importance of the Research Achievements

世界最先端の超高速SFQプロセッサアーキテクチャとその回路設計を通じて、世界初となる数々の動作実証に成功した。これらの成果は、今後の超伝導コンピューティングを支える要素技術として大きな成果である。また、データセンターなど情報処理における電力消費(その結果として二酸化炭素排出量)の増大は、地球環境負荷の観点から深刻な問題となってる。これに対し、本研究で取り組んだ超伝導コンピューティングはポストムーア時代を支える超高性能かつ超低消費電力な情報処理プラットフォームを実現する有望な候補の一つであり、今後の情報技術の世界的普及と浸透を鑑みた場合、大きな社会的意義を持つ。

Report

(5 results)
  • 2021 Annual Research Report   Final Research Report ( PDF )
  • 2020 Annual Research Report
  • 2019 Comments on the Screening Results   Annual Research Report
  • Research Products

    (63 results)

All 2022 2021 2020 2019 Other

All Int'l Joint Research (3 results) Journal Article (5 results) (of which Int'l Joint Research: 1 results,  Peer Reviewed: 4 results,  Open Access: 1 results) Presentation (55 results) (of which Int'l Joint Research: 22 results,  Invited: 18 results)

  • [Int'l Joint Research] Seoul National University(韓国)

    • Related Report
      2021 Annual Research Report
  • [Int'l Joint Research] Seoul National University(韓国)

    • Related Report
      2020 Annual Research Report
  • [Int'l Joint Research] Seoul National University(韓国)

    • Related Report
      2019 Annual Research Report
  • [Journal Article] Superconductor Computing for Neural Networks2021

    • Author(s)
      Ishida Koki、Byun Ilkwon、Nagaoka Ikki、Fukumitsu Kosuke、Tanaka Masamitsu、Kawakami Satoshi、Tanimoto Teruo、Ono Takatsugu、Kim Jangwoo、Inoue Koji
    • Journal Title

      IEEE Micro

      Volume: 41 Issue: 3 Pages: 1-8

    • DOI

      10.1109/mm.2021.3070488

    • Related Report
      2021 Annual Research Report
    • Peer Reviewed / Open Access / Int'l Joint Research
  • [Journal Article] Demonstration of a 52-GHz Bit-Parallel Multiplier Using Low-Voltage Rapid Single-Flux-Quantum Logic2021

    • Author(s)
      I. Nagaoka, K. Ishida, M. Tanaka, K. Sano, T. Yamashita, T. Ono, K. Inoue, and A. Fujimaki
    • Journal Title

      IEEE Transactions on Applied Superconductivity

      Volume: TBD Issue: 5 Pages: 1-5

    • DOI

      10.1109/tasc.2021.3071996

    • Related Report
      2021 Annual Research Report
    • Peer Reviewed
  • [Journal Article] 64-GHz datapath demonstration for bit-parallel SFQ microprocessors based on a gate-level-pipeline structure2021

    • Author(s)
      Ryota Kashima, Ikki Nagaoka, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki
    • Journal Title

      IEEE Transactions on Applied Superconductivity

      Volume: 31-5 Issue: 5 Pages: 1301006-1301006

    • DOI

      10.1109/tasc.2021.3061353

    • Related Report
      2021 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Investigation of Timing Parameters in Single-Flux-Quantum Circuits Using Low Critical-Current Junctions and Low Bias Voltages2021

    • Author(s)
      M. Kuniyoshi, K. Murase, I. Nagaoka, K. Sano, M. Tanaka, T. Yamashita, and A. Fujimaki
    • Journal Title

      IEEE Transactions on Applied Superconductivity

      Volume: 31 Issue: 5 Pages: 1101405-1101405

    • DOI

      10.1109/tasc.2021.3067827

    • Related Report
      2021 Annual Research Report
    • Peer Reviewed
  • [Journal Article] ムーアの法則の限界が見えた今,デバイス研究はどこに向かうのか ―コンピュータアーキテクチャの視点から―2019

    • Author(s)
      井上弘士, 川上哲志, 田中雅光
    • Journal Title

      電子情報通信学会誌

      Volume: 102 Pages: 957-962

    • NAID

      40022043682

    • Related Report
      2019 Annual Research Report
  • [Presentation] 単一磁束量子回路の面積削減へ向けた細線受動伝送線路用ビアホールの設計と評価2022

    • Author(s)
      加島亮太, 長岡一起, 田中雅光, 山下太郎, 藤巻朗
    • Organizer
      2022年電子情報通信学会総合大会
    • Related Report
      2021 Annual Research Report
  • [Presentation] 単一磁束量子回路に基づくゲートレベルパイプライン浮動小数点演算器の動作実証2022

    • Author(s)
      長岡一起, 加島亮太, 田中雅光, 川上哲志, 谷本輝夫, 山下太郎, 井上弘士, 藤巻朗
    • Organizer
      2022年電子情報通信学会総合大会
    • Related Report
      2021 Annual Research Report
  • [Presentation] Towards Extremely High-Speed, Low-Power Cryogenic Superconductor Computing2022

    • Author(s)
      Koji Inoue
    • Organizer
      CRNCH (Center for Research into Novel Computing Hierarchies) Summit
    • Related Report
      2021 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device2022

    • Author(s)
      Iori Ishikawa, Ikki Nagaoka, Ryota Kashima, Koki Ishida, Kosuke Fukumitsu, Keitaro Oka, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Akira Fujimaki, Koji Inoue
    • Organizer
      he IEEE International Symposium on Circuits and Systems (ISCAS)
    • Related Report
      2021 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Implementation of a High-Throughput Bit-Parallel Microprocessor Using Single-Flux-Quantum Logic2021

    • Author(s)
      I. Nagaoka, R. Kashima, T. Nakano, M. Tanaka, T. Yamashita, and A. Fujimaki
    • Organizer
      15th European Conference on Applied Superconductivity (EUCAS 2021)
    • Related Report
      2021 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] 10kA/cm2プロセスを用いた単一磁束子100GHzビット並列加算器の実証2021

    • Author(s)
      中埜智貴, 長岡一起, 加島亮太, 田中雅光, 山下太郎, 藤巻朗
    • Organizer
      第82回応用物理学会秋季学術講演会
    • Related Report
      2021 Annual Research Report
  • [Presentation] 単一磁束量子回路に基づくゲートレベルパイプライン浮動小数点演算器の設計2021

    • Author(s)
      長岡一起, 加島亮太, 田中雅光, 山下太郎, 川上哲志, 井上弘士, 藤巻朗
    • Organizer
      2021年電子情報通信学会ソサイエティ大会
    • Related Report
      2021 Annual Research Report
  • [Presentation] アンシャント接合による加算器の高速化2021

    • Author(s)
      国吉真波, 長岡一起, 田中雅光, 山下太郎, 藤巻朗
    • Organizer
      2021年電子情報通信学会ソサイエティ大会
    • Related Report
      2021 Annual Research Report
  • [Presentation] 低レイテンシ化を目的としたインターリーブ方式レジスタを伴う単一磁束量子データパスの動作実証2021

    • Author(s)
      加島亮太, 長岡一起, 中埜智貴, 田中雅光, 山下太郎, 藤巻朗
    • Organizer
      2021年電子情報通信学会ソサイエティ大会
    • Related Report
      2021 Annual Research Report
  • [Presentation] 単一磁束量子回路によるビット幅可変加減算器の設計と評価2021

    • Author(s)
      石川伊織, 長岡 一起, 石田浩貴, 福光孝介, 岡慶太郎, 田中雅光, 川上哲志, 谷本輝夫, 小野貴継, 藤巻朗, 井上 弘士
    • Organizer
      情報処理学会システムアーキテクチャ研究会
    • Related Report
      2021 Annual Research Report
  • [Presentation] Ultra-Fast, Low-Power Neural Network Computing with Superconductor Devices2021

    • Author(s)
      Koji Inoue
    • Organizer
      Brain-Inspired Computing: Physics, Architectures, Materials, and Applications
    • Related Report
      2021 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] SIMD演算に適したブロック構造を有する新しいILU分解前処理手法2021

    • Author(s)
      鈴木謙吾, 深谷猛, 岩下武史
    • Organizer
      The 5th cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG 2021)
    • Related Report
      2021 Annual Research Report
  • [Presentation] 低消費電力単一磁束量子回路の動作周波数の調査2021

    • Author(s)
      国吉真波, 村瀬健, 長岡一起, 田中雅光, 山下太郎, 藤巻朗
    • Organizer
      電子情報通信学会超伝導エレクトロニクス研究会
    • Related Report
      2020 Annual Research Report
  • [Presentation] アンシャント接合によるSFQ論理ゲートのエネルギー効率の向上2021

    • Author(s)
      国吉真波, 長岡一起, 田中雅光, 山下太郎, 藤巻朗
    • Organizer
      電子情報通信学会2021年総合大会
    • Related Report
      2020 Annual Research Report
  • [Presentation] 単一磁束量子回路に基づく50GHzビット並列演算マイクロプロセッサの設計2021

    • Author(s)
      長岡一起, 加島亮太, 中埜智貴, 田中雅光, 山下太郎, 藤巻朗
    • Organizer
      電子情報通信学会2021年総合大会
    • Related Report
      2020 Annual Research Report
  • [Presentation] 単一磁束量子回路の高集積化へ向けた細線受動伝送線路の評価2021

    • Author(s)
      加島亮太, 長岡一起, 田中雅光, 山下太郎, 藤巻朗
    • Organizer
      電子情報通信学会2021年総合大会
    • Related Report
      2020 Annual Research Report
  • [Presentation] 超伝導ニューラルネットワーク・アクセラレータのアーキテクチャ探索を目的とした電力性能モデリング2021

    • Author(s)
      石田浩貴, IlkwonByun, 長岡一起, 福光孝介, 田中雅光, 川上哲志, 谷本輝夫, 小野貴継, 藤巻朗, Jangwoo Kim, 井上弘士
    • Organizer
      情報処理学会 236回システム・アーキテクチャ研究会
    • Related Report
      2020 Annual Research Report
  • [Presentation] 近未来のコンピューティング像を探る!2021

    • Author(s)
      井上弘士
    • Organizer
      産総研 IMPULSE コンソーシアム 2020年度第4回セミナー
    • Related Report
      2020 Annual Research Report
    • Invited
  • [Presentation] Towards Ultra-High-Speed Superconductor Computing ~ Computer Architecture Perspective ~2021

    • Author(s)
      Koji Inoue
    • Organizer
      the 33rd International Superconductivity Symposium (ISS2020)
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] Challenges in Ultra-High-Performance Low-Power Computing towards the Post Moore Era ~ A Computer Architecture Perspective ~2021

    • Author(s)
      Koji Inoue
    • Organizer
      26th Asia and South Pacific Design Automation Conference ASP-DAC 2021
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] 32 GHz 6.5 mW gate-level-pipelined 4-bit processor using superconductor single-flux-quantum logic2020

    • Author(s)
      K. Ishida, M. Tanaka, I. Nagaoka, T. Ono, S. Kawakami, T. Tanimoto, A. Fujimaki, and K. Inoue
    • Organizer
      2020 IEEE Symposium on VLSI Circuits
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 単一磁束量子回路に基づく並列処理データパスの 64GHz動作実証2020

    • Author(s)
      加島亮太, 長岡一起, 田中雅光, 山下太郎, 藤巻朗
    • Organizer
      2020年電子情報通信学会ソサイエティ大会
    • Related Report
      2020 Annual Research Report
  • [Presentation] 低消費電力単一磁束量子回路における論理ゲートのタイミングパラメータ解析2020

    • Author(s)
      国吉真波, 長岡一起, 田中雅光, 山下太郎, 藤巻朗
    • Organizer
      2020年電子情報通信学会ソサイエティ大会
    • Related Report
      2020 Annual Research Report
  • [Presentation] フィードバックループを含む単一磁束量子回路の高周波設計に向けたカウンターフロー方式シフトレジスタのタイミング解析2020

    • Author(s)
      長岡一起, 加島亮太, 田中雅光, 山下太郎, 藤巻朗
    • Organizer
      2020年電子情報通信学会ソサイエティ大会
    • Related Report
      2020 Annual Research Report
  • [Presentation] SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices2020

    • Author(s)
      K. Ishida, I. Byun, I. Nagaoka, K. Fukumitsu, M. Tanaka, S. Kawakami, T. Tanimoto, T. Ono, J. Kim, and K. Inoue
    • Organizer
      53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Demonstration of a 52-GHz, energy-efficient, bit-parallel multiplier using low-voltage rapid single-flux-quantum logic2020

    • Author(s)
      I. Nagaoka, K. Ishida, M. Tanaka, K. Sano, T. Yamashita, T. Ono, K. Inoue, and A. Fujimaki
    • Organizer
      Applied Superconductivity Conference (ASC 2020)
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] High-density routing with wire length matching for single-flux-quantum circuits using thin passive transmission lines2020

    • Author(s)
      K. Kitamura, M. Tanaka, T. Kawaguchi, I. Nagaoka, K. Takagi, A. Fujimaki, and N. Takagi
    • Organizer
      Applied Superconductivity Conference (ASC 2020)
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Investigation of timing parameters in single flux quantum circuits using low critical current junctions and low bias voltages2020

    • Author(s)
      M. Kuniyoshi, K. Murase, I. Nagaoka, K. Sano, M. Tanaka, T. Yamashita, and A. Fujimaki
    • Organizer
      Applied Superconductivity Conference (ASC 2020)
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 50-GHz datapath for parallel SFQ microprocessors based on gate-level-pipeline architecture2020

    • Author(s)
      R. Kashima, I. Nagaoka, M. Tanaka, K. Sano, T. Yamashita, and A. Fujimaki
    • Organizer
      Applied Superconductivity Conference (ASC 2020)
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 50-GHz datapath for parallel SFQ microprocessors based on gate-level-pipeline architecture2020

    • Author(s)
      M. Tanaka, M. Kuniyoshi, K. Murase, I. Nagaoka, T. Yamashita, and A. Fujimaki
    • Organizer
      2nd Workshop on Quantum and Classical Cryogenic Devices, Circuits, and Systems (QCCC 2020)
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] アーキテクチャ探索を目的とした単一磁束量子回路の電力効率モデリング2020

    • Author(s)
      福光孝介, 石田浩貴, 長岡一起, 田中雅光, 川上哲志, 谷本輝夫, 小野貴継, 藤巻朗, 井上弘士
    • Organizer
      情報処理学会研究報告, Vol.2020-ARC-242 No.5, pp.1-7
    • Related Report
      2020 Annual Research Report
  • [Presentation] 単一磁束量子回路を用いた4ビットゲートレベルパイプライン・プロセッサの設計2020

    • Author(s)
      石田浩貴
    • Organizer
      VDECデザインコンテスト
    • Related Report
      2020 Annual Research Report
  • [Presentation] 単一磁束量子回路を用いたニューラルネットワーク・アクセラレータのプロトタイプ設計2020

    • Author(s)
      福光孝介
    • Organizer
      VDECデザインコンテスト
    • Related Report
      2020 Annual Research Report
  • [Presentation] An Integer Arithmetic-Based Sparse Linear Solver Using a GMRES Method and Iterative Refinement2020

    • Author(s)
      Takeshi Iwashita, Kengo Suzuki and Takeshi Fukaya
    • Organizer
      Conference Proceedings of 2020 IEEE/ACM 11th Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (ScalA)
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] An Iterative Refinement Technique with an Integer Arithmetic-Based GMRES Solver2020

    • Author(s)
      Takeshi Iwashita
    • Organizer
      Lip6(仏 ソルボンヌ大学, CNRS)PEQUAN team seminar
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] 革新的コンピューティングの実現に向けた新デバイス技術への期待2020

    • Author(s)
      井上弘士
    • Organizer
      第一回 阪大スピンセンター異分野交流研究会
    • Related Report
      2020 Annual Research Report 2019 Annual Research Report
    • Invited
  • [Presentation] Development of 50-GHz, high-throughput rapid single-flux-quantum circuits toward ultra-fast, energy-efficient computing2020

    • Author(s)
      M. Tanaka
    • Organizer
      10th Asian Conference on Applied Superconductivity and Cryogenics (ACASC), 2nd International Cryogenic Materials Conference in Asia (Asian-ICMC), and CSSJ Joint Conference
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] Challenges to thermal limit, quantum limit, and high throughput based on SFQ circuits2020

    • Author(s)
      A. Fujimaki
    • Organizer
      2020 International Symposium on Superconductor Electronics / 13th Superconducting SFQ VLSI Workshop
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] Design of datapath for 8 bit parallel SFQ microprocessors with gate level pipelines2020

    • Author(s)
      R. Kashima
    • Organizer
      2020 International Symposium on Superconductor Electronics / 13th Superconducting SFQ VLSI Workshop
    • Related Report
      2019 Annual Research Report
    • Invited
  • [Presentation] Investigation of timing design by using low-power SFQ shift registers2020

    • Author(s)
      M. Kuniyoshi
    • Organizer
      2020 International Symposium on Superconductor Electronics / 13th Superconducting SFQ VLSI Workshop
    • Related Report
      2019 Annual Research Report
    • Invited
  • [Presentation] High-throughput gate-level-pipelined SFQ multipliers2020

    • Author(s)
      I. Nagaoka
    • Organizer
      2020 International Symposium on Superconductor Electronics / 13th Superconducting SFQ VLSI Workshop
    • Related Report
      2019 Annual Research Report
    • Invited
  • [Presentation] Development of gate-level-pipelined SFQ circuits toward ultra-high-speed cryogenic computing2020

    • Author(s)
      M. Tanaka
    • Organizer
      2020 International Symposium on Superconductor Electronics / 13th Superconducting SFQ VLSI Workshop
    • Related Report
      2019 Annual Research Report
    • Invited
  • [Presentation] 単一磁束量子回路に基づく50 GHz並列処理データパスの設計2020

    • Author(s)
      加島亮太
    • Organizer
      電子情報通信学会2020年総合大会
    • Related Report
      2019 Annual Research Report
  • [Presentation] 低電圧駆動単一磁束量子回路における論理ゲートのタイミングパラメータの解析2020

    • Author(s)
      国吉真波
    • Organizer
      電子情報通信学会2020年総合大会
    • Related Report
      2019 Annual Research Report
  • [Presentation] 単一磁束量子回路に基づく低電圧駆動ゲートレベルパイプライン算術論理演算器の設計と評価2020

    • Author(s)
      長岡一起
    • Organizer
      電子情報通信学会2020年総合大会
    • Related Report
      2019 Annual Research Report
  • [Presentation] Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core2020

    • Author(s)
      Susumu Mashimo
    • Organizer
      International Conference on High Performance Computing in Asia-Pacific Region
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] nhancing a manycore-oriented compressed cache for GPGPU2020

    • Author(s)
      Keitaro Oka
    • Organizer
      nternational Conference on High Performance Computing in Asia-Pacific Region
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 100TOPS/W超伝導単一磁束量子演算器2019

    • Author(s)
      長岡一起
    • Organizer
      LSIとシステムのワークショップ2019
    • Related Report
      2019 Annual Research Report
  • [Presentation] 単一磁束量子回路に基づくゲートレベル・パイプライン算術論理演算器の高エネルギー効率化と0.3mW, 30GHz動作実証2019

    • Author(s)
      田中雅光
    • Organizer
      2019年並列/分散/協調処理に関する『北見』サマー・ワークショップ(SWoPP2019)
    • Related Report
      2019 Annual Research Report
  • [Presentation] 単一磁束量子回路に基づく低電圧駆動ゲートレベルパイプライン算術論理演算器の設計と評価2019

    • Author(s)
      長岡一起
    • Organizer
      電子情報通信学会2019年ソサイエティ大会
    • Related Report
      2019 Annual Research Report
  • [Presentation] Towards Ultra High-Speed Superconducting Computing2019

    • Author(s)
      K. Inoue
    • Organizer
      the 19th International Forum on Embedded MPSoC and Multicore
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] 革新的コンピューティングの創生に向けて~量的変化から質的変化へ~2019

    • Author(s)
      井上弘士
    • Organizer
      IPSJ連続セミナー
    • Related Report
      2019 Annual Research Report
    • Invited
  • [Presentation] 次世代超伝導コンピューティング2019

    • Author(s)
      井上弘士
    • Organizer
      応用物理学会
    • Related Report
      2019 Annual Research Report
    • Invited
  • [Presentation] An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor2019

    • Author(s)
      Susumu Mashimo
    • Organizer
      IEEE International Conference on Field Programmable Technology
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] An Efficient SAT-Attack Algorithm Against Logic Encryption2019

    • Author(s)
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    • Organizer
      International Symposium on On-Line Testing and Robust System Design (IOLTS)
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research

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Published: 2019-04-18   Modified: 2023-01-30  

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