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Development of methods for testing and diagnosing faults on clock lines in system LSIs

Research Project

Project/Area Number 22500048
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionEhime University

Principal Investigator

HIGAMI Yoshinobu  愛媛大学, 大学院・理工学研究科, 准教授 (40304654)

Co-Investigator(Kenkyū-buntansha) TAKAHASHI Hiroshi  愛媛大学, 大学院・理工学研究科, 教授 (80226878)
Project Period (FY) 2010 – 2012
Project Status Completed (Fiscal Year 2012)
Budget Amount *help
¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000)
Fiscal Year 2012: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2011: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2010: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Keywordsディペンダブルコンピューティング / 論理回路の故障検査 / LSIの故障診断 / 故障検査 / システムLSI / クロック信号線 / 遅延故障 / テストパターン生成 / LSIの設計・テスト / 故障診断 / 論理回路
Research Abstract

:I n this research, we have developed a testing and a diagnosis method for system LSIs. Targets are delay faults and bridging faults on clock lines. The method locates a fault site in a circuit under diagnosis, and it applies a simulation-based approach. The effectiveness of the method are confirmed by the computer simulation for benchmark circuits.

Report

(4 results)
  • 2012 Annual Research Report   Final Research Report ( PDF )
  • 2011 Annual Research Report
  • 2010 Annual Research Report

Research Products

(12 results)

All 2012 2011 2010

All Journal Article Presentation

  • [Journal Article] Generation of Diagnostic Tests for Transition Faults Using a Stuck-at ATPG Tool2012

    • Author(s)
      Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
    • Journal Title

      IEICE Trans. on Inf. & Systems

      Volume: vol. E95-D Pages: 1093-1100

    • NAID

      10030942163

    • Related Report
      2012 Final Research Report
  • [Journal Article] Diagnosis of Bridging Faults at Gated Clock Lines2012

    • Author(s)
      Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
    • Journal Title

      Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications

    • Related Report
      2012 Final Research Report
  • [Journal Article] Diagnosis for Bridging Faults on Clock Lines2012

    • Author(s)
      Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
    • Journal Title

      Proc. Pacific Rim Int. Symposium on Dependable Computing

    • DOI

      10.1109/prdc.2012.15

    • Related Report
      2012 Final Research Report
  • [Journal Article] Generation of Diagnostic Tests for Transition Faults Using a Stuck-at ATPG Tool2012

    • Author(s)
      Yoshinobu Higami
    • Journal Title

      IEICE Trans. on Information and Systems

      Volume: E95-D Pages: 1093-1100

    • NAID

      10030942163

    • Related Report
      2012 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Diagnosis of Bridging Faults at Gated Clock Lines2012

    • Author(s)
      Yoshinobu Higami
    • Journal Title

      Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications

      Volume: -

    • Related Report
      2012 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Diagnosis for Bridging Faults on Clock Lines2012

    • Author(s)
      Yoshinobu Higami
    • Journal Title

      Proc. Pacific Rim Int. Symposium on Dependable Computing

      Volume: - Pages: 135-144

    • Related Report
      2012 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Enhancement of Clock Delay Faults Testing2011

    • Author(s)
      Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
    • Journal Title

      Proc. European Test Symposium

    • DOI

      10.1109/ets.2011.27

    • Related Report
      2012 Final Research Report 2011 Annual Research Report
  • [Journal Article] On Detecting Transition Faults in the Presence of Clock Delay Faults2011

    • Author(s)
      Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
    • Journal Title

      Proc. Asian Test Symposium

      Pages: 1-6

    • DOI

      10.1109/ats.2011.33

    • Related Report
      2012 Final Research Report 2011 Annual Research Report
  • [Journal Article] Fault Simulation and Test Generation for Clock Delay Faults2011

    • Author(s)
      Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
    • Journal Title

      Proc. Asia and South Pacific Design Automation Conference

      Pages: 799-805

    • DOI

      10.1109/aspdac.2011.5722299

    • Related Report
      2012 Final Research Report
  • [Journal Article] Fault Simulation and Test Generation for Clock Delay Faults2011

    • Author(s)
      Y.Higami, H.Takahashi, S.Kobayashi, K.K.Saluja
    • Journal Title

      Proc.of Asia and South Pacific Design Automation Conference

      Pages: 799-805

    • Related Report
      2010 Annual Research Report
    • Peer Reviewed
  • [Presentation] クロック信号線の遅延故障に対するテスト生成について2010

    • Author(s)
      樋上喜信, 高橋寛, 小林真也, Kewal K.Saluja
    • Organizer
      FTC研究会
    • Place of Presentation
      埼玉県秩父郡
    • Year and Date
      2010-07-16
    • Related Report
      2010 Annual Research Report
  • [Presentation] FTC 研究会2010

    • Author(s)
      樋上喜信,高橋寛,小林真也,Kewal K. Saluja
    • Organizer
      クロック信号線の遅延故障に対するテスト生成について
    • Related Report
      2012 Final Research Report

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Published: 2010-08-22   Modified: 2019-07-29  

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