Low Power Techniques of Network-on-Chips for Many-core Computer Platforms
| Project/Area Number |
22700061
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | National Institute of Informatics |
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Principal Investigator |
KOIBUCHI Michihiro 国立情報学研究所, アーキテクチャ科学研究系, 准教授 (40413926)
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| Project Period (FY) |
2010-04-01 – 2014-03-31
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000)
Fiscal Year 2012: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2011: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2010: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
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| Keywords | ネットワークオンチップ / 低消費電力技術 / システムオンチップ / 相互結合網 / メニーコア / トポロジー / 計算機システム |
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| Research Abstract |
In this study our objective is to present innovative dynamic low-power and low-latency techniques of network-on-chips for many-core processor platforms that form IT equipments, such as mobile terminals and high-performance computers. Our main solutions are (1) low-power variable pipeline-and-frequency on-chip routers (1 cycle to 4 cycles) optimized to traffic load, (2) its dynamic reconfiguration techniques and (3) random topology design of routers whose link length is limited within 6 core logical length. Their efficiency is confirmed via full-system simulation and power estimation.
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Report
(4 results)
Research Products
(18 results)
