Design Methodology for Dependable Logic Circuits with Small Overhead
| Project/Area Number |
23300019
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Ritsumeikan University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
冨山 宏之 立命館大学, 理工学部, 教授 (80362292)
吉田 浩章 東京大学, 大規模集積システム設計教育研究センタ, 助教 (10456163)
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| Co-Investigator(Renkei-kenkyūsha) |
原 祐子 東京工業大学, 理工学研究科, 准教授 (20640999)
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| Project Period (FY) |
2011-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥18,590,000 (Direct Cost: ¥14,300,000、Indirect Cost: ¥4,290,000)
Fiscal Year 2014: ¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2013: ¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2012: ¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2011: ¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
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| Keywords | PPC / 製造時故障 / 仕様変更 / 耐故障 / 高位合成 / LUT / ディペンダブル・コンピューティング / バイオチップ / 故障 / フィルムコンピュータ |
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| Outline of Final Research Achievements |
We have studied various design methodology for dependable logic circuits by utilizing the model of PPCs (Partially Programmable Circuits) which contains LUTs. Our main research result is concerning circuits which can bypass some manufacturing faults with less overhead compared with conventional methods. Our research achievement includes (1) design methods of PPCs, (2) how to reduce the area cost of LUTs without changing the ability to bypass faults, (3) how to utilize PPCs for engineering change, (4) verification methods of PPCs, and (5) high-level synthesis with functional units by PPCs.
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Report
(5 results)
Research Products
(58 results)
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[Presentation] "Novel Area-Efficient Technique for Yield Improvement
Author(s)
Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, and Yasuhiko Nakashima
Organizer
Electronic System-Level Design towards Heterogeneous Computing in conjunction with Design, Automation & Test in Europe (DATE)
Place of Presentation
Dresden, Germany
Related Report
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