| Budget Amount *help |
¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2015: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2014: ¥2,860,000 (Direct Cost: ¥2,200,000、Indirect Cost: ¥660,000)
Fiscal Year 2013: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
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| Outline of Final Research Achievements |
In this research, we designed and verified our realistic microarchitecture of CoreSymphony in hardware description language which enables efficient cooperative core features on multi-core processors. In other words, we reduced the required hardware cost for CoreSymphony processors using sophisticated microarchitecture techniques. Moreover, in order to develop an FPGA (field-programmable gate array) board for computer architecture research, high-speed serial communication between FPGA boards with serial ATA cables is evaluated and confirmed its high data bandwidth and we designed original FPGA board with this high-speed serial communication, FPGA, and DRAM chip.
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