Timing failure diagnosis using pre-silicon test and post-silicon test
| Project/Area Number |
25330063
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Ehime University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
樋上 喜信 愛媛大学, 理工学研究科(工学系), 教授 (40304654)
四柳 浩之 徳島大学, 大学院理工学研究部, 准教授 (90304550)
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| Project Period (FY) |
2013-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2015: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2014: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2013: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
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| Keywords | ディペンダブルコンピューティング / 故障検査 / 故障診断 / オープン故障 / タイミング不良 / テスト / 診断 / オンチップセンサー / 抵抗性オープン故障 / ポストシリコンテスト / プリシリコンテスト / 故障診断法 / 診断用テスト / 遅延故障 / 組込み自己テスト / 組込み自己診断 |
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| Outline of Final Research Achievements |
It is difficult for the existing methods for the stuck-at faults and the transition delay faults to guarantee the quality of the high-speed system on chips. In this study, we proposed a concept of 2 pattern-2 pair tests as a high quality diagnostic test for resistive open faults. Also we proposed methods for generating the diagnostic tests by using SAT solver and the Simulated Annealing. We proposed an on-chip sensor that is applied by the analog boundary-scan as a design-for diagnosis. Moreover, we proposed a diagnostic method based on the ranking of the sensitized paths. From the experimental results for the benchmark circuits, we show that the proposed methods can generate the high quality diagnostic tests and the proposed diagnosis method can obtain the better diagnostic resolutions compared with the existing methods.
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Report
(5 results)
Research Products
(30 results)
