| 研究課題/領域番号 |
21K04191
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| 研究種目 |
基盤研究(C)
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| 配分区分 | 基金 |
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| 応募区分 | 一般 |
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| 審査区分 |
小区分21060:電子デバイスおよび電子機器関連
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| 研究機関 | 横浜国立大学 |
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研究代表者 |
アヤラ クリストファー 横浜国立大学, 先端科学高等研究院, 特任教員(准教授) (90772195)
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| 研究期間 (年度) |
2021-04-01 – 2024-03-31
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| 研究課題ステータス |
交付 (2022年度)
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| 配分額 *注記 |
4,030千円 (直接経費: 3,100千円、間接経費: 930千円)
2023年度: 1,040千円 (直接経費: 800千円、間接経費: 240千円)
2022年度: 1,040千円 (直接経費: 800千円、間接経費: 240千円)
2021年度: 1,950千円 (直接経費: 1,500千円、間接経費: 450千円)
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| キーワード | superconductor / crypto / computing / adiabatic / sfq / aqfp / cryotron / nanowire / monolithic integration / energy-efficient / accelerators |
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| 研究開始時の研究の概要 |
We will explore various emerging superconductor electronics to realize a practical path towards novel hybrid superconductor computing platforms that can meet the demands of today's data centric society with performance and energy-efficiency beyond what is possible with conventional technology.
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| 研究実績の概要 |
In this year we investigated the co-integration of different superconductor logic families in a hybrid manner. We developed a standard cell layout architecture for building hybrid AC/DC-biased logic circuits (10.1109/TASC.2023.3258366). This cell layout architecture is the groundwork in which we can assemble different logic families together on the same chip with appropriate interfacing circuits in a very systematic manner. Next, we developed an demonstrated logic interfacing circuits to exchange data between logic families (10.1109/TASC.2023.3244147). This updated design is more robust compared to previous iterations and even uses a more modern manufacturing process. Then, we developed low-latency hybrid serializers/deserializers (10.1109/ACCESS.2022.3230447). These circuits serve as facilities for data communication between components as well as off-chip transmission. These are excellent examples of synergetic integration between different logic families leveraging their respective strengths. We also looked at important details for scaling up our technology such as issues with signal integrity (10.1109/TASC.2023.3239828) and large-scale clock skew (10.1088/1361-6668/aca3d6). We proposed a candidate architecture for a cryptoprocessor for hybrid integration and demonstrated a major component up to 7 GHz. The work was selected to be featured in Superconductivity News Forum (SNF), Issue No. 52, March 2023.
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| 現在までの達成度 (区分) |
現在までの達成度 (区分)
2: おおむね順調に進展している
理由
The main tasks were (1) to conduct an analysis and develop a methodology to support the co-integration of emerging superconductor technologies, and (2) to consider an appropriate accelerator architecture with small scale demonstrations. The published articles in FY2022 have addressed a lot of task (1). Unfortunately, some emerging technologies such as nanowire cryotrons were not able to be pursued as deeply as expected due to unforeseen constraints in the independent budgets of our collaborators working on this technology. We will still try to pursue these directions. On the other hand, we made a lot of progress in task (2) by demonstrating a complex component of a crypto accelerator at record operating frequencies resulting in an invitation to be featured in SNF.
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| 今後の研究の推進方策 |
The focus for FY2023 is to build a more complete crypto-accelerator prototype by fully utilizing the methodologies developed in the past year. It should have a complexity of about 10k-20k devices and operate at GHz clock frequencies. We will also make attempts to dive deeper into nanowire cryotron integration with our independently funded collaborators as we were not able to do so this year. We plan to summarize our challenges and outline comprehensively design automation needs for VLSI scaling. We plan to present results at the European Conference on Applied Superconductivity (EUCAS 2023), the International Symposium on Superconductivity (ISS 2023), and either the International Solid-State Circuits Conference (ISSCC 2024) or the Symposium on VLSI Technology and Circuits (2024).
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