| 研究実績の概要 |
In this final year, we continued to develop methodologies and demonstrated key components for a synergistic system design of superconductor logic families. This includes a collaborative investigation with a world-class group at the Swiss Federal Institute of Technology Lausanne where a tool was developed to create optimal sequential logic circuits based on AQFP technology (10.1109/TASC.2023.3308408). To address synchronization between different logic families, a deeper characterization of the timing behavior of AQFP logic was developed (10.1109/TASC.2024.3352638). This will pave way for in-depth timing characterization of other logic families that will be co-integrated with AQFP and would increase the likelihood of successful circuit demonstration. On the end of improving the likelihood demonstrating large circuits, the analysis of circuit malfunctions due to unwanted flux trapping was performed (10.1109/TASC.2024.3354687). Thanks to this analysis, a new layout for AQFP gates with integration moats to protect the circuit from trapped flux was developed with significantly improved robustness against trapped flux. A number of to-be-published results have been produced including (1) the demonstration of combining sinusoidal and trapezoidal clocking for sequential circuits, (2) the demonstration of a large scale SHA-3 cryptoprocessing accelerator at GHz operation speeds based on using the methods and techniques developed in this research, and (3) conceptual development of a hybrid logic architecture that shows promise in the application of post-quantum cryptography.
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