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[文献書誌] Tetsuhisa Mido: "TEST Structure for Characterizing Capacitance Matrix of Multi-layer Interconnections in VLSI"IEICE Trans., Electronics. Vol. E82-C. No.4. 570-575 (1999)
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[文献書誌] M. Ikeda: "Standard Design Flows of Logic LSIs in Japanese Universities and VDEC"Proc. of MSE 99. 8-9 (1999)
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[文献書誌] K. Asada: "Approaches for Reducing Power Consumption in VLSI Bus Circuits"IEICE Trans., Electron. Vol. E83-C. No.2. 153-160 (2000)
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[文献書誌] H. Aoki: "On-Chip Voltage Noise Mouitor for Measuring Voltage Bounce in Power Supply Lines Using a Disital Tester"Proc. of ICMTS 2000. (掲載予定). (2000)
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[文献書誌] M. Ikeda: "DVDT : Design for Voltage Drop Test using Onchip-Voltage Scan Path"Proc. of ISQED 2000. No.2(掲載予定). (2000)
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[文献書誌] M.Ikeda: "A New Trial on HDL Exercise Class for Undergraduate School in EE Department"Proc.Of EWME 2000. (掲載予定). (2000)