Studies on Layout Design Methods for Logic Circuits using Superconducting Devices

2017 Fiscal Year Final Research Report

• Project/Area Number: 15K00075
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Kyoto University
• Principal Investigator: Kazuyoshi Takagi 京都大学, 情報学研究科, 准教授 (70273844)
• Project Period (FY): 2015-04-01 – 2018-03-31
• Keywords: 論理回路 / 設計自動化 / 超伝導単一磁束量子デバイス

Outline of Final Research Achievements

We studied layout design methods for superconducting single-flux-quantum logic circuits which can realize super high-speed and low-power consumption digital circuits. (1) We developed a channel routing method considering wire-length matching for precise adjustment of pulse arrival timing. (2) We proposed a new circuit design flow in which logic design and delay optimization are performed separately. In the logic design stage, we describe the circuit topology as well as the order of pulse arrival at each logic gate and the target operation frequency. In layout design, placement and routing are performed with minimizing circuit delay under the condition of the operation frequency. (3) We proposed usages of circuit design tools according to the design flow of (2), and developed related tools.

Free Research Field

計算機科学