Circuit technology and architecture for ultralow-power high-speed integrated circuits using beyond-CMOS devices

2023 Fiscal Year Final Research Report

• Project/Area Number: 20K21791
• Research Category: Grant-in-Aid for Challenging Research (Exploratory)
• Allocation Type: Multi-year Fund
• Review Section: Medium-sized Section 60:Information science, computer engineering, and related fields
• Research Institution: Tokyo Institute of Technology
• Principal Investigator: Sugahara Satoshi 東京工業大学, 科学技術創成研究院, 准教授 (40282842)
• Project Period (FY): 2020-07-30 – 2024-03-31
• Keywords: 集積回路 / Beyond-CMOS / ultralow voltage

Outline of Final Research Achievements

Ultra-low voltage operations of complementally CMOS logic systems are considerably effective at reducing power dissipation. However, their operation speed is severely degraded for the ultralow-voltage operations, since the current drivability of the transistors deteriorates at low voltages. A new piezoelectronic transistor (PET) is proposed for ultralow-voltage high-speed integrated circuits. The device is comprised of a cylindrical piezoresistive (PR) channel and a torus-shape piezoelectric (PE) gate. The PR channel can largely change its resistivity owing to the metal-insulator transition. The PET can achieve high current drivability even at ultralow voltages. Design methodologies and architectures of complementary-PET-based basic circuits for logic applications are developed. Performance and behavior of these PET-based circuits are analyzed using an equivalent circuit of PETs. The complementary PETs can exhibit high-speed (several GHz operations) and low-power performance at 0.2 V.

Free Research Field

集積回路

Academic Significance and Societal Importance of the Research Achievements

本研究課題では，Beyond-CMOSの一つであるpiezoelectronic transistor (PET)をモデルケースとして，超低電圧駆動GHz級動作が可能な超低消費電力・高速ロジックシステムの基盤技術の開発を行った．本研究で開発した技術のようにPETと同様の高い電流駆動能力を有するBeyond-CMOSであれば，超低電圧であってもCMOSとほぼコンパチブルな回路技術・アーキテクチャを共通に応用できる可能性がある．