2013 Fiscal Year Final Research Report
Understanding of carrier transport mechanism in Ge MOS interfaces and establishment of mobility enhancement technologies
| Project/Area Number |
23246058
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | The University of Tokyo |
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Principal Investigator |
TAKAGI Shinichi 東京大学, 工学(系)研究科(研究院), 教授 (30372402)
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| Co-Investigator(Renkei-kenkyūsha) |
TAKENAKA Mitsuru 東京大学, 大学院工学系研究科, 准教授 (20451792)
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| Project Period (FY) |
2011-04-01 – 2014-03-31
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| Keywords | MOSFET / ゲルマニウム / 移動度 / 反転層 / サブバンド |
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| Research Abstract |
We have clarified from comparison between effective and Hall mobility of Ge MOSFETs that inversion-layer carriers are trapped into interface states locating inside the conduction and valence bands, leading to the reduction in the effective mobility. Also, atomic deuterium annealing is fond to reduce the interface states and to increase the effective mobility. Also, HfO2/Al2O3/GeOx/Ge MOSFETs with EOT of 0.76 nm, realized by ECR plasma oxidation, exhibited peak electron and hole mobility of 690 and 550 cm2/Vs, respectively. The surface orientation dependence of the effective mobility has also been revealed. In addition, we demonstrated GOI n- and p-MOSFETs with GOI thinner than 20 nm, fabricated by the Ge condensation and Ge wafer bonding, and evaluated the mobility behaviors.
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[Journal Article] High Mobility CMOS Technologies using III-V/Ge Channels on Si platform2013
Author(s)
S.Takagi, S.-H.Kim, M.Yokoyama, R.Zhang, N.Taoka, Y.Urabe, T.Yasuda, H.Yamada, O.Ichikawa, N.Fukuhara, M.Hata and M.Takenaka
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Journal Title
Solid State Electronics
Volume: Vol.88
Pages: 2-8
DOI
Peer Reviewed
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[Presentation] III-V/Ge CMOS device technologies2013
Author(s)
S.Takagi and M.Takenaka
Organizer
20th Symposium on Nano Device Technology (SNDT)
Place of Presentation
International Conference Hall of Nano Device Laboratory, Hsinchu, Taiwan
Year and Date
20130425-26
Invited
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[Presentation] MOS interface control in III-V/Ge gate stacks and the impact on MOSFET performance2013
Author(s)
S.Takagi, R.Zhang, N.Taoka, R.Suzuki, S.-H.Kim, M.Yokoyama, and M.Takenaka
Organizer
2013 MRS (Material Research Society) Spring Meeting, Symposium CC "Gate Stack Technology for End-of-Roadmap Devices in Logic, Power, and Memory"
Place of Presentation
Moscone Center, San Francisco, USA
Year and Date
20130401-05
Invited
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