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2013 Fiscal Year Final Research Report

Design of dependable Analog Mixed-Signal LSI with intermittent operation of fault detection system

Research Project

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Project/Area Number 23500067
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Computer system/Network
Research InstitutionKochi University of Technology

Principal Investigator

TACHIBANA Masayoshi  高知工科大学, 工学部, 教授 (50171715)

Project Period (FY) 2011 – 2013
Keywordsディペンダブルコンピューティング / Analog Mixed-Signal
Research Abstract

We propose fault-based BIST(Built-In Self Test) schemes for Anlog part of AMS(Analog Mixed-Signal) system LSI. The BIST systems can be used throughout life time of LSIs, from fabrication process to the system's operation. The motif of analog system to design BIST system is Anlog-to-Digital or Digital-to-Analog data convertor which is commonly used sub-system in AMS LSI systems.
We chose 3 types of circuits which compose the data convertor, which are R-2R ladder type Digital-to-Analog convetor, Fully-differential sample-and-hold circuit, and Operational Amplifers with different architectures. The BIST systems are based on transient respose of circuits and fault coverage for Caterstrofic faults, such like open/short fault of circuit elements, are about 86% to 96% with resonable area overhead.

  • Research Products

    (4 results)

All 2013 2012 2011

All Journal Article (2 results) Presentation (2 results)

  • [Journal Article] A resister matching based self-testable current-mode R-2R digital-to-analog converter2013

    • Author(s)
      Yuan Jun, Masayoshi Tachibana
    • Journal Title

      IEICE Electronics Express

      Volume: Vol.10, No.23 Pages: 1-7

    • DOI

      10.1587/elex.10.20130753

  • [Journal Article] A common-mode BIST technique for fully- differential sample-and-hold circuits2012

    • Author(s)
      Yuan Jun, Masayoshi Tachibana
    • Journal Title

      IEICE Electronics Express

      Volume: Vol.9, No.13 Pages: 1128-1134

    • DOI

      10.1587/elex.9.1128

  • [Presentation] A two-Step BIST Scheme for Operational Amplifier2012

    • Author(s)
      Yuan Jun, Masayoshi Tachibana
    • Organizer
      Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2011)
    • Place of Presentation
      Beppu, Oita, Japan
    • Year and Date
      2012-03-09
  • [Presentation] A BIST Scheme for Amplifier by Checking the Stable output of Transient Response2011

    • Author(s)
      Yuan Jun, Masayoshi Tachibana
    • Organizer
      The 20th European Conference on Circuit Theory and Design
    • Place of Presentation
      Linkoeping, Sweden
    • Year and Date
      2011-08-31

URL: 

Published: 2015-07-16  

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