Nano MOSFET Fluctuations and Device Integrity

• Project/Area Number: 18063006
• Research Category: Grant-in-Aid for Scientific Research on Priority Areas
• Allocation Type: Single-year Grants
• Review Section: Science and Engineering
• Research Institution: The University of Tokyo
• Principal Investigator: HIRAMOTO Toshiro The University of Tokyo, 生産技術研究所, 教授 (20192718)
• Co-Investigator(Kenkyū-buntansha): 更屋 拓哉 東京大学, 生産技術研究所, 助手 (90334367)
• Co-Investigator(Renkei-kenkyūsha): SARAYA Takuya 東京大学, 生産技術研究所, 助手 (90334367)
• Project Period (FY): 2006 – 2009
• Project Status: Completed (Fiscal Year 2009)
• Budget Amount: ¥51,200,000 (Direct Cost: ¥51,200,000); Fiscal Year 2009: ¥13,800,000 (Direct Cost: ¥13,800,000); Fiscal Year 2008: ¥13,800,000 (Direct Cost: ¥13,800,000); Fiscal Year 2007: ¥11,800,000 (Direct Cost: ¥11,800,000); Fiscal Year 2006: ¥11,800,000 (Direct Cost: ¥11,800,000)
• Keywords: 特性ばらつき / しきい値電圧 / SOI / SRAM / MOSFET / 半導体 / 不純物揺らぎ / 微細化 / VLSI / ランダムテレグラフノイズ / 正規分布 / 半導体超微細化 / 基板バイアス効果 / 低消費電力 / 不純物ゆらぎ

Research Abstract

Random variability has been studied by measurements and simulation. It has been clarified that SOI MOSFETs with very thin buried oxide is less sensitive to random dopant fluctuations. A new method of self-suppression of variability after chip fabrication has been proposed and its validity has been demonstrated by simulation.

Research Products

• [Journal Article] Threshold Voltage Dependence of Threshold Voltage Variability in Intrinsic Channel Silicon-on-Insulator (2010)
  • Author(s): C.Lee, A.T.Putra, K.Shimizu, T.Hiramoto
  • Journal Title: No.4, Issue 2
  • Peer Reviewed
• [Journal Article] Threshold Voltage Dependense of Threshold Voltage Variability in Intrinsic Channel Silioon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors with Ultrathin Buried Oxide (2010)
  • Author(s): Chiho Lee
  • Journal Title: Japanese Journal of Applied Physics Volume: 49
  • Peer Reviewed
• [Journal Article] Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal-Oxide-Semiconductor Field-Effect-Transistors (2009)
  • Author(s): A.T.Putra, T.Tsunomura, A.Nishida, S.Kamohara, K.Takeuchi, T.Hiramoto
  • Journal Title: Japanese Journal of Applied Physics Vol.48, No.6 Pages: 64504-64504
  • Peer Reviewed
• [Journal Article] MOSトランジスタのスケーリングに伴う特性ばらつき (2009)
  • Author(s): 平本俊郎, 竹内潔, 西田彰男
  • Journal Title: 電子情報通信学会会誌 Vol.92, No.6 Pages: 416-426
  • NAID: 110007227367
  • Peer Reviewed
• [Journal Article] Consideration of Random Dopant Fluctuation Models for Accurate Prediction of Threshold Voltage Variation of Metal-Oxide-Semiconductor Field-Effect Transistors in 45nm Technology and Beyond (2009)
  • Author(s): A.T.Putra, A.Nishida, S.Kamohara, T.Tsunomura, T.Hiramoto
  • Journal Title: Japanese Journal of Applied Physics Vol.48, No.4 Pages: 44502-44502
  • Peer Reviewed
• [Journal Article] Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal-Oxide-Semiconductor Field-Effect Transistors (2009)
  • Author(s): A.T.Putra, A.Nishida, S.Kamohara, T.Hiramoto
  • Journal Title: Applied Physics Express Vol.2, No.2 Pages: 24501-24501
  • Peer Reviewed
• [Journal Article] Random Threshold Voltage Variability Induced by Gate Edge Fluctuations in Nanoscale Metal-Oxide- Semiconductor Field-Effect-Transistors (2009)
  • Author(s): A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto
  • Journal Title: Applied Physics Express Vol. 2, No. 2 Pages: 24501-24501
• [Journal Article] Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal-Oxide-Semiconductor Field-Effect Transistors (2009)
  • Author(s): Arifin Tamsir Putra, Akio Nishida, Shim Kamohara, and Toshiro Hiramoto
  • Journal Title: Applied Physics Express 2 Pages: 24501-24501
  • Peer Reviewed
• [Journal Article] 増大する微細MOSトランジスタの特性ばらつき:現状と対策 (2008)
  • Author(s): 平本俊郎, 竹内潔, 西田彰男
  • Journal Title: 電気学会論文誌C Vol.128, No.6 Pages: 820-824
  • NAID: 10021132489
  • Peer Reviewed
• [Journal Article] Variable Body-Factor SOI MOSFET with Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control (2008)
  • Author(s): T.Ohtou, T.Saraya, T.Hiramoto
  • Journal Title: IEEE Transactions on Electron Devices vol.54, no.1 Pages: 40-46
  • Peer Reviewed
• [Journal Article] Variable Body-Factor SOI MOSFET with Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control (2008)
  • Author(s): T. Ohtou, T. Saraya, and T. Hiramoto
  • Journal Title: IEEE Transactions on Electron Devices(Invited) vol. 54, no. 1 Pages: 40-46
• [Journal Article] Variable Body-Factor SOI MOSFET with Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control (2008)
  • Author(s): Tetsu Ohtou, Takuya Saraya, and Toshiro Hiramoto
  • Journal Title: IEEE Transactions on Electron Devices 54 Pages: 40-46
  • Peer Reviewed
• [Journal Article] Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX (2007)
  • Author(s): T.Ohtou, N.Sugii, T.Hiramoto
  • Journal Title: IEEE Electron Devices Letters Vol.28, No.8 Pages: 740-742
  • Peer Reviewed
• [Journal Article] Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations (2007)
  • Author(s): T.Hiramoto, T.Nagumo, T.Ohtou, K.Yokoyama
  • Journal Title: IEICE Transactions on Electronics Vol.E90-C, No.4 Pages: 836-841
  • Peer Reviewed
• [Journal Article] Threshold-Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme (2007)
  • Author(s): T.Ohtou, K.Yokoyama, K.Shimizu, T.Nagumo, T.Hiramoto
  • Journal Title: IEEE Transactions on Electron Devices Vol.54, No.2 Pages: 301-307
  • Peer Reviewed
• [Journal Article] Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX (2007)
  • Author(s): T. Ohtou, N. Sugii, and T. Hiramoto
  • Journal Title: IEEE Electron Devices Letters Vol. 28, No. 8 Pages: 740-742
• [Journal Article] Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations (2007)
  • Author(s): T. Hiramoto, T. Nagumo, T. Ohtou, and K. Yokoyama
  • Journal Title: IEICE Transactions on Electronics(Invited) Vol. E90-C, No. 4 Pages: 836-841
• [Journal Article] Threshold- Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme (2007)
  • Author(s): T. Ohtou, K. Yokoyama, K. Shimizu, T. Nagumo, and T. Hiramoto
  • Journal Title: IEEE Transactions on Electron Devices Vol. 54, No. 2 Pages: 301-307
• [Journal Article] Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX (2007)
  • Author(s): Tetsu Ohtou, Nobuyuki Sugii, and Toshiro Hiramoto
  • Journal Title: IEEE Electron Devices Letters 28 Pages: 740-742
  • Peer Reviewed
• [Journal Article] Threshold-Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme (2007)
  • Author(s): T.Ohtou, K.Yokoyama, K.Shimizu, T.Nagumo, T.Hiramoto
  • Journal Title: IEEE Transactions on Electron Devices Vol. 54, No. 2 Pages: 301-307
• [Journal Article] Design Guideline of Multi-Gate MOSFETs With Substrate-Bias Control (2006)
  • Author(s): T.Nagumo, T.Hiramoto
  • Journal Title: IEEE Transactions on Electron Devices Vol.53, No.12 Pages: 3025-3031
  • Peer Reviewed
• [Journal Article] Modeling of Body Factor and Subthreshold Swing in Bulk Metal Oxide Semiconductor Field Effect Transistors in Short-Channel Regime (2006)
  • Author(s): A.T.Putra, M.Saitoh, G.Tsutsui, T.Hiramoto
  • Journal Title: Japanese Journal of Applied Physics Vol.45, No.8A Pages: 6173-6176
  • Peer Reviewed
• [Journal Article] Design Guideline of Multi-Gate MOSFETs with Substrate-Bias Control (2006)
  • Author(s): T. Nagumo and T. Hiramoto
  • Journal Title: IEEE Transactions on Electron Devices Vol. 53, No. 12 Pages: 3025-3031
• [Journal Article] Modeling of Body Factor and Subthreshold Swing in Bulk Metal Oxide Semiconductor Field Effect Transistors in Short-Channel Regime (2006)
  • Author(s): A.T.Putra, M.Saitoh, G.Tsutsui, T.Hiramoto
  • Journal Title: Japanese Journal of Applied Physics Vol. 45, No. 8A Pages: 6173-6176
• [Journal Article] Mobility and Threshold-Voltage Comparison Between (110)-and (100)-Oriented Ultrathin-Body Silicon MOSFETs (2006)
  • Author(s): G.Tsutsui, T.Hiramoto
  • Journal Title: IEEE Transactions on Electron Devices Vol. 53, No. 10 Pages: 2582-2588
• [Journal Article] Design Guideline of Multi-Gate MOSFETs With Substrate-Bias Control (2006)
  • Author(s): T.Nagumo, Toshiro Hiramoto
  • Journal Title: IEEE Transactions on Electron Devices Vol. 53, No. 12 Pages: 3025-3031
• [Presentation] 完全欠乏型SOI MOSFETにおけるDIBLおよび"電流立上がり電圧"ばらつきの抑制 (2011)
  • Author(s): 水谷朋子
  • Organizer: 2011年春季第58回応用物理学学術講演会
  • Place of Presentation: 神奈川工科大学
  • Year and Date: 2011-03-26
• [Presentation] 完全欠乏型SOI MOSFETにおけるランダムテレグラフノイズの抑制 (2011)
  • Author(s): 西村淳
  • Organizer: 2011年春季第58回応用物理学学術講演会
  • Place of Presentation: 神奈川工科大学
  • Year and Date: 2011-03-26
• [Presentation] Statistical Comparison of Random Telegraph Noise (RTN) in Bulk and Fully Depleted SOI MOSFETs (2011)
  • Author(s): J.Nishimura, T.Saraya, T.Hiramoto
  • Organizer: Ultimate Integration of Silicon (ULIS)
  • Place of Presentation: Cork, Ireland
  • Year and Date: 2011-03-16
• [Presentation] Statistical Comparision of Random Telegraph Noise(RTN) in Bulk and Fully Depleted SOI MOSFETs (2011)
  • Author(s): Jun Nishimura
  • Organizer: Ultimate Integration of Silicon (ULIS)
  • Place of Presentation: アイルランド・コーク
  • Year and Date: 2011-03-16
• [Presentation] Suppression of DIBL and Current-Onset Voltage Variability in Intrinsic Channnel Fully Depleted SOI MOSFETs (2010)
  • Author(s): T.Hiramoto
  • Organizer: IEEE International SOI Conference
  • Place of Presentation: 米国・サンディエゴ
  • Year and Date: 2010-10-14
• [Presentation] Measurements and characterization of statistical variability (2010)
  • Author(s): T.Hiramoto
  • Organizer: Workshop on Simulation and Characterization of Statistical CMOS Variability and Reliability, The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
  • Place of Presentation: Royal Hotel Carlton, Bologna, Italy
  • Year and Date: 2010-09-09
• [Presentation] Effect of Back Bias on Variability in Intrinsic Channel SOI MOSFETs (2010)
  • Author(s): T.Hiramoto, T.Saraya, C.Lee
  • Organizer: International Symposium on Technology Evolution for Silicon Nano-Electronics (ISTESNE)
  • Place of Presentation: Tokyo Institute of Technology
  • Year and Date: 2010-06-03
• [Presentation] SRAMにおける読み/書き込みマージン一括自己修復手法 (2010)
  • Author(s): 鈴木誠
  • Organizer: 2010年春季第57回応用物理学学術講演会
  • Place of Presentation: 東海大学湘南キャンパス
  • Year and Date: 2010-03-17
• [Presentation] Simultaneously improvement of Write and Static Noise Margins in SRAM by Post-Fabrication Self-Convergence Technique (2010)
  • Author(s): M.Suzuki, T.Saraya, K.Shimizu, T.Sakurai, T.Hiramoto
  • Organizer: Workshop "The Fruits of Variability Research in Europe", Design, Automation & Test in Europe (DATE)
  • Place of Presentation: International Congress Centre in Dresden, Dresden, Germany
  • Year and Date: 2010-03-12
• [Presentation] Variability research : accomplishments and future directions-a Japanese perspective (2010)
  • Author(s): T.Hiramoto
  • Organizer: Workshop "The Fruits of Variability Research in Europe", Design, Automation & Test in Europe (DATE)
  • Place of Presentation: International Congress Centre in Dresden, Dresden, Germany
  • Year and Date: 2010-03-12
• [Presentation] Simultaneously improvement of Write and Static Noise Margins in SRAM by Post-Fabrication Self-Convergence (2010)
  • Author(s): Makoto Suzuki
  • Organizer: Workshop "The Fruits of Variability Research in Europe" Design、Automation & Test in Europe(DATE)
  • Place of Presentation: ドイツ・ドレスデン
  • Year and Date: 2010-03-12
• [Presentation] Improvement of Static Noise Margin in SRAM by Post-Fabrication Self-Convergence Technique (2009)
  • Author(s): M.Suzuki, T.Saraya, K.Shimizu, T.Sakurai, T.Hiramoto
  • Organizer: International Semiconductor Device Research Symposium (ISDRS), TP7-03
  • Place of Presentation: University of Maryland, MD, USA
  • Year and Date: 2009-12-10
• [Presentation] Improvement of Static Noise Margin SRAM by Post-Fabrication Self-Convergence Technique (2009)
  • Author(s): Makoto Suzuki
  • Organizer: International Semiconductor Deveice Research Symposium (ISDRS)
  • Place of Presentation: 米国・メリーランド大学
  • Year and Date: 2009-12-10
• [Presentation] Anomalous Back-Bias Dependence of Threshold Voltage Variability in NMOSFETs Due to High Concentration Regions near Source and Drain (2009)
  • Author(s): I.Yamato, T.Mama, T.Tsunomura, A.Nishida, T.Hiramoto
  • Organizer: International Semiconductor Device Research Symposium (ISDRS), WP5-04
  • Place of Presentation: University of Maryland, MD, USA
  • Year and Date: 2009-12-09
• [Presentation] Vth Dependence of Vth Variability in Intrinsic Channel SOI MOSFETs with Ultra-Thin BOX (2009)
  • Author(s): C.Lee, A.T.Putra, K.Shimizu, T.Hiramoto
  • Organizer: International Conference on Solid State Devices and Materials (SSDM)
  • Place of Presentation: Sendai
  • Year and Date: 2009-10-07
• [Presentation] ロジックトランジスタにおける特性ばらつき一括自己修復手法 (2009)
  • Author(s): 鈴木誠
  • Organizer: 第70回応用物理学会学術講演会
  • Place of Presentation: 富山大学
  • Year and Date: 2009-09-08
• [Presentation] SRAMにおける特性ばらつき一括自己修復手法 (2009)
  • Author(s): 鈴木誠
  • Organizer: 第70回応用物理学会学術講演会
  • Place of Presentation: 富山大学
  • Year and Date: 2009-09-08
• [Presentation] SRAMおよびロジックトランジスタにおける特性ばらつき一括自己修復手法 (2009)
  • Author(s): 鈴木誠
  • Organizer: 応用物理学会シリコンテクノロジー分科会研究集会
  • Place of Presentation: 東京大学
  • Year and Date: 2009-07-21
• [Presentation] Post-Fabrication Self-Convergence Scheme for Suppressing Variability in SRAM Cells and Logic Transistors (2009)
  • Author(s): M.Suzuki, T.Saraya, K.Shimizu, T.Sakurai, T.Hiramoto
  • Organizer: Symposium on VLSI Technology, pp.148-149
  • Place of Presentation: Kyoto
  • Year and Date: 2009-06-16
• [Presentation] A New Methodology for Evaluating VT Variability Considering Dopant Depth Profile (2009)
  • Author(s): A.T.Putra, T.Tsunomura, A.Nishida, S.Kamohara, K.Takeuchi, S.Inaba, K.Terada, T.Hiramoto
  • Organizer: Symposium on VLSI Technology, pp.116-117
  • Place of Presentation: Kyoto
  • Year and Date: 2009-06-16
• [Presentation] Post-Fabrication Self-Convergence Scheme for Suppressing Variability in SRAM Cells and Logic Transistors (2009)
  • Author(s): Makoto Suzuki
  • Organizer: Symposium on VLSI Technology
  • Place of Presentation: 京都
  • Year and Date: 2009-06-16
• [Presentation] Impact of Lateral Dopant Profile on Threshold Voltage Variability in Scaled MOSFETs (2009)
  • Author(s): I.Yamato, A.T.Putra, T.Hiramoto
  • Organizer: Silicon Nanoelectronics Workshop, pp.35-36
  • Place of Presentation: Kyoto
  • Year and Date: 2009-06-13
• [Presentation] Characterization of CMOS Variability Utilizing 1M-DMA and Takeuchi Plot (2008)
  • Author(s): T.Hiramoto
  • Organizer: Workshop on Test Structure Design for Variability Characterization
  • Place of Presentation: DoulbleTree Hotel, San Jose, CA, USA
  • Year and Date: 2008-11-13
• [Presentation] Measuring and Understanding Device Variability (2008)
  • Author(s): T.Hiramoto
  • Organizer: ESSDER/ ESSIRC Variability Workshop
  • Place of Presentation: Edinburgh International Conference Centre, Edinburgh, UK
  • Year and Date: 2008-09-19
• [Presentation] Impact of Fixed Charge at MOSFETs' SiO2/Si Interface on Vth Variation (2008)
  • Author(s): A.T.Putra, T.Tsunomura, A.Nishida, S.Kamohara, K.Takeuchi, T.Hiramoto
  • Organizer: International Conference on Simulation of Semiconductor Devices and Processes (SISPAD)
  • Place of Presentation: Hakone Prince Hotel, Kanagawa, Japan
  • Year and Date: 2008-09-09
• [Presentation] Mobility and Variability in Silicon Nanowire MOSFETs (2008)
  • Author(s): T.Hiramoto, M.Kobayashi, J.Chen
  • Organizer: 14th International Symposium on the Physics of Semiconductors and Applications (ISPSA-2008), p.192
  • Place of Presentation: Korea, Ramada Plaza Jeju Hotel, Jeju
  • Year and Date: 2008-08-27
• [Presentation] Impact of Atomic Oxide Roughness and Local Gate Depletion on Vth Variation in MOSFETs (2008)
  • Author(s): A.T.Putra, T.Tsunomura, A.Nishida , S.Kamohara, K.Takeuchi, T.Hiramoto
  • Organizer: IEEE Silicon Nanoelectronics Workshop, S1205
  • Place of Presentation: Hilton Hawaiian Village, HI, USA
  • Year and Date: 2008-06-15
• [Presentation] Impact of Fixed Charge at MOSFETs' SiO2/Si Interface on Vth Variation (2008)
  • Author(s): A.T. Putra, T. Tsunomura, A. Nishida, S. Kamohara, K. Takeuchi, and T. Hiramoto
  • Organizer: International Conference on Simulation of Semiconductor Devices and Processes
  • Place of Presentation: 神奈川県箱根町
  • Year and Date: 2008-04-09
• [Presentation] FinFETs with Both Large Body Factor and High Drive-Current (2007)
  • Author(s): K.Takahashi, A.T.Putra, T.Hiramoto
  • Organizer: International Semiconductor Device Research Symposium (ISDRS), WP9-01-11
  • Place of Presentation: University of Maryland, MD, USA
  • Year and Date: 2007-12-12
• [Presentation] Impact of Local Poly-Si Gate Depletion on Vth Variation in Nanoscale MOSFETs Investigated by 3D Device Simulation (2007)
  • Author(s): A.T.Putra, A.Nishida, S.Kamohara, T.Tsunomura, T.Hiramoto
  • Organizer: International Semiconductor Device Research Symposium (ISDRS), WP8-03
  • Place of Presentation: University of Maryland, MD, USA
  • Year and Date: 2007-12-12
• [Presentation] Robust Design of Transistors : Present Status and Measures to Characteristic Variations (2007)
  • Author(s): T.Hiramoto
  • Organizer: 2007 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD 2007), pp.5-8
  • Place of Presentation: Commodore Hotel Gyeongju Chosun, Korea
  • Year and Date: 2007-06-25
• [Presentation] Body Factor and Leakage Current Reduction in Bulk FinFETs (2007)
  • Author(s): K.Takahashi, T.Ohtou, A.T.Putra, K.Shimizu, T.Hiramoto
  • Organizer: Silicon Nanoelectronics Workshop, pp.95-97
  • Place of Presentation: Rihga Royal Hotel Kyoto
  • Year and Date: 2007-06-10
• [Presentation] Random Vth Variation Induced by Gate Edge Fluctuations in Nanoscale MOSFETs (2007)
  • Author(s): A.T.Putra, A.Nishida, S.Kamohara, T.Hiramoto
  • Organizer: Silicon Nanoelectronics Workshop, pp.73-74
  • Place of Presentation: Rihga Royal Hotel Kyoto
  • Year and Date: 2007-06-10
• [Presentation] Characteristics Variation in Silicon Nanowire Transistors (2007)
  • Author(s): T.Hiramoto, M.Kobayashi
  • Organizer: 3rd International Nanotechnology Conference on Communication and Cooperation
  • Place of Presentation: Brussels, Bergium
  • Year and Date: 2007-04-17
• [Presentation] Experimental Demonstrations of Superior Characteristics of Variable Body-Factor (γ) Fully-Depleted SOI MOSFETs with Extremely Thin BOX of 10nm (2006)
  • Author(s): T.Ohtou, T.Saraya, K.Shimokawa, Y.Doumae, Y.Nagatomo, J.Ida, T.Hiramoto
  • Organizer: IEEE International Electron Devices Meeting (IEDM), pp.877-880
  • Place of Presentation: San Francisco, CA, USA
  • Year and Date: 2006-12-13
• [Presentation] Experimental Study on Quantum Structure of Silicon Nano Wire and Its Impact on Nano Wire MOSFET and Single-Electron Transistor (2006)
  • Author(s): M.Kobayashi, T.Hiramoto
  • Organizer: Technical Digests of IEEE International Electron Devices Meeting (IEDM), pp.1007-1009
  • Place of Presentation: San Francisco, CA, USA
  • Year and Date: 2006-12-11
• [Presentation] Critical Substrate Bias in Variable-Threshold Voltage CMOS with Short Channel FD SOI MOSFETs (2006)
  • Author(s): A.T.Putra, T.Ohtou, T.Hiramoto
  • Organizer: IEEE Silicon Nanoelectronics Workshop, pp.159-160
  • Place of Presentation: Honolulu, HI, USA
  • Year and Date: 2006-06-12
• [Presentation] Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully-Depleted SOI MOSFETs with Extremely Thin BOX (2006)
  • Author(s): T.Ohtou, N.Sugii, T.Hiramoto
  • Organizer: IEEE Silicon Nanoelectronics Workshop, pp.15-16
  • Place of Presentation: Honolulu, HI, USA
  • Year and Date: 2006-06-11
• [Presentation] Multi-Gate MOSFETs with Back-Gate Control (2006)
  • Author(s): T.Hiramoto, T.Nagumo
  • Organizer: 2006 International Conference on Integrated Circuit Design and Technology (ICICDT), pp.80-81
  • Place of Presentation: Padova University, Padova, Italy
  • Year and Date: 2006-05-25
• [Book] 集積ナノデバイス (2009)
  • Author(s): 平本俊郎, 内田建, 竹内潔, 杉井信之
  • Publisher: 丸善
• [Patent(Industrial Property Rights)] ラッチ回路の電圧特性調整方法および半導体装置の電圧特性調整方法 (2009)
  • Inventor(s): 平本俊郎, 鈴木誠, 桜井貴康
  • Industrial Property Rights Holder: 東京大学
  • Industrial Property Number: 2009-141510
  • Filing Date: 2009-06-12
• [Patent(Industrial Property Rights)] ラッチ回路の電圧特性調整方法および半導体装置の電圧特性調整方法 (2009)
  • Inventor(s): 平本俊郎
  • Industrial Property Rights Holder: 東京大学
  • Industrial Property Number: 2009-141510
  • Filing Date: 2009-06-12