| Budget Amount *help |
¥15,770,000 (Direct Cost: ¥12,800,000、Indirect Cost: ¥2,970,000)
Fiscal Year 2009: ¥5,720,000 (Direct Cost: ¥4,400,000、Indirect Cost: ¥1,320,000)
Fiscal Year 2008: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2007: ¥5,720,000 (Direct Cost: ¥4,400,000、Indirect Cost: ¥1,320,000)
Fiscal Year 2006: ¥2,900,000 (Direct Cost: ¥2,900,000)
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| Research Abstract |
Scientific calculations such as Loop integrals and CG methods require multiple-precision floating-point operations. In this project, to achieve faster multiple-precision floating-point operations used in these applications, we propose HP-DSFP architecture. In HP-DSFP architecture, by using the digit-serial computation scheme, we achieved 2.4 times higher performance compared with the conventional arithmetic unit using the same chip area.
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