Super-Low-Operating-Voltage Dependable SRAM Using Total Variability Suppression Effects in FD-SOI
| Project/Area Number |
20360161
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Kobe University |
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Principal Investigator |
KAWAGUCHI Hiroshi 神戸大学, 大学院・システム情報学研究科, 准教授 (00361642)
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| Project Period (FY) |
2008 – 2011
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| Project Status |
Completed (Fiscal Year 2011)
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| Budget Amount *help |
¥18,330,000 (Direct Cost: ¥14,100,000、Indirect Cost: ¥4,230,000)
Fiscal Year 2011: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2010: ¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2009: ¥9,490,000 (Direct Cost: ¥7,300,000、Indirect Cost: ¥2,190,000)
Fiscal Year 2008: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
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| Keywords | SRAM / ディペンダブルVLSI / ばらつき / 低電圧動作 / FD-SOI |
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| Research Abstract |
We proposed a substrate bias control scheme for an FD-SOI SRAM that suppresses inter-die variability and a 7T/14T(7-transistor/14-transistor) memory cell that can be dynamically compensate its intra-die variability. The proposed substrate bias control circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 150-nm 486-kb FD-SOI SRAM operates at 0. 42 V, in which an FS corner can be compared as much as 0. 14 V. For the 7T/14T dependable memory cell verification, we fabricated a 150-nm 576-kb FD-SOI SRAM. The 14T dependable mode allocates one bit in a 14T cell and improves its bit error rate. In our measurements, the minimum retention voltage and the minimum operating voltage were reduced by 150 mV and 320 mV in the 14T dependable mode over the 7T normal mode, respectively.
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Report
(6 results)
Research Products
(42 results)
