A study on establishment of a theory for accelerating computation based on partial-computation using FPGAs
| Project/Area Number |
20700030
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Software
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| Research Institution | Hiroshima University |
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Principal Investigator |
ITO Yasuaki 広島大学, 大学院・工学研究院, 助教 (40397964)
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| Project Period (FY) |
2008 – 2011
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| Project Status |
Completed (Fiscal Year 2011)
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| Budget Amount *help |
¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2011: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2010: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2009: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2008: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
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| Keywords | FPGA / ハード・ソフト協調設計 |
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| Research Abstract |
In this study, we have tried to establish a theory of accelerating computation using FPGA based on the notion of partial computation. Partial computation is a computing technique to reduce computing time by fixing a part of parameters of a problem. For various problems that have a property of the partial computation, such as image halftoning, image component labeling, verification of Collatz conjecture, and RSA encryption, we achieved accelerating solutions using FPGAs(Field Programmable Gate Arrays) that are programmable VLSIs.
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Report
(6 results)
Research Products
(25 results)
