Low-Power High-Speed Table Lookup Processing in Routers

2017 Fiscal Year Final Research Report

• Project/Area Number: 16H06798
• Research Category: Grant-in-Aid for Research Activity Start-up
• Allocation Type: Single-year Grants
• Research Field: Communication/Network engineering
• Research Institution: The University of Electro-Communications
• Principal Investigator: Yamaki Hayato 電気通信大学, 大学院情報理工学研究科, 助教 (20782197)
• Project Period (FY): 2016-08-26 – 2018-03-31
• Keywords: ルータ / パケット処理 / 高スループット / 省電力化 / キャッシュ

Outline of Final Research Achievements

This study proposed more efficient cache control mechanism for Packet Processing Cache (PPC), which enabled to process packets at high speed with significant low energy, and evaluated the hardware costs. First, we enabled to improve the cache hit rate of PPC from 70% to 80% to adopt a speculative packet processing method which stored processing results of packets into the cache in advance. In addition, we simulated and evaluated the hardware implementation of our approach and showed that our approach can be implemented with implementable hardware costs.

Free Research Field

計算機アーキテクチャ