Large tiled display system with virtualized GPU

Research Project

Project/Area Number	24500108
Research Category	Grant-in-Aid for Scientific Research (C)
Allocation Type	Multi-year Fund
Section	一般
Research Field	Media informatics/Database
Research Institution	The University of Electro-Communications
Principal Investigator	Narumi Tetsu 電気通信大学, 情報理工学(系)研究科, 教授 (10342825)
Project Period (FY)	2012-04-01 – 2016-03-31
Project Status	Completed (Fiscal Year 2015)
Budget Amount *help	¥5,330,000 (Direct Cost: ¥4,100,000、Indirect Cost: ¥1,230,000) Fiscal Year 2014: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000) Fiscal Year 2013: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000) Fiscal Year 2012: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Keywords	タイルドディスプレイ / FPGA / ティアリング / GPU仮想化 / 計算機システム / ディスプレイ
Outline of Final Research Achievements	We developed a cost-effective tiled display system by designing a custom FPGA board instead of using professional equipments. Since it is composed by a hardware, tearing cannot be happen. Actually, we made sure that the timing difference between displays are very small because it worked with stereo display using shutter glasses which is very sensitive to synchronization of displays. Also we developed a software to support remote OpenGL rendering by extending DS-CUDA middleware which virtualizes remote GPUs.

Report

(5 results)